US6557145B2
Expired / Lapsed
US
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Method for design optimization using logical and physical information
Assignee: Synopsys Inc
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Filing: 2001-03-06
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Granted: 2003-04-29
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Expires: 2021-03-06
Abstract
Abstract A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
Inventors
- 👤 Douglas B. Boyle
- 👤 James S. Koford
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:24
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F30/39; G06F30/398; G06F2119/00; G06F2119/06
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
89 words
A method for design optimization, comprising the steps of: placing circuit elements of a design; providing routing or routing estimates for said design; and performing logic optimization on said design, said steps of placing, providing and performing logic optimization are performed concurrently for at least a portion of time, wherein one of said steps of placing, providing and performing logic optimization is performed on one portion of said design while another of said steps of placing, providing and performing logic optimization is performed on another portion of said design.
Claim 2
Independent Claim
89 words
A method for design optimization, comprising the steps of: placing circuit elements of a design; providing routing or routing estimates for said design; and performing logic optimization on said design, said steps of placing, providing and performing logic optimization are performed concurrently for at least a portion of time, wherein one of said steps of placing, providing and performing logic optimization is performed on one portion of said design while another of said steps of placing, providing and performing logic optimization is performed on another portion of said design.
Claim 3
Dependent Claim
52 words
A method according to claim 1 , wherein: said step of placing is performed on a first portion of said design while said step of providing is performed on a second portion of said design and while said step of performing logic optimization is performed on a third portion of said design.
Claim 4
Dependent Claim
41 words
A method according to claim 1 , further comprising the step of: performing a timing analysis and a power analysis on said design concurrently, for at least a portion of time, with said steps of placing, providing and performing logic optimization.
Claim 5
Dependent Claim
94 words
A method according to claim 1 , further comprising the steps of: dividing elements of said design into clusters; performing an initial placement and routing estimation of said design prior to said steps of placing, providing and performing logic optimization; and performing an inner loop and an outer loop, said inner loop includes performing said steps of placing, providing and performing logic optimization on a current set of clusters, said outer loop includes reducing cluster size and performing said inner loop on said reduced clusters until said cluster size is at a predefined level.
Claim 6
Dependent Claim
37 words
A method according to claim 1 , further comprising the step of: performing a timing analysis on said design concurrently, for at least a portion of time, with said steps of placing, providing and performing logic optimization.
Claim 7
Dependent Claim
37 words
A method according to claim 1 , further comprising the step of: performing a power analysis on said design concurrently, for at least a portion of time, with said steps of placing, providing and performing logic optimization.
Claim 8
Dependent Claim
22 words
A method according to claim 1 , wherein: said steps of placing, providing and performing logic optimization are performed by parallel processors.
Claim 9
Dependent Claim
46 words
A method according to claim 1 , wherein: said step of placing is performed by a first parallel processor while said step of providing is performed by a second parallel processor and while said step of performing logic optimization is performed by a third parallel processor.
Claim 10
Dependent Claim
73 words
A method according to claim 8 , wherein: said step of placing is performed on a first set of one or more clusters of elements of said design while said step of providing is performed on a second set of one or more clusters of elements of said design and while said step of performing logic optimization is performed on a third set of one or more clusters of elements of said design.
Claim 11
Dependent Claim
31 words
A method according to claim 9 , further comprising the step of: performing a timing analysis on said design in parallel with said steps of placing, providing and performing logic optimization.
Claim 12
Dependent Claim
21 words
A method according to claim 1 , wherein: said step of performing logic optimization includes providing alternative implementations of logic circuits.
Claim 13
Dependent Claim
18 words
A method according to claim 1 , wherein: said step of performing logic optimization includes insertions of buffers.
Claim 14
Dependent Claim
114 words
A processor readable storage device having processor readable code embodied on said processor readable storage device, said processor readable code for programming one or more processors to perform a method comprising the steps of: placing circuit elements of a design; providing routing or routing estimates for said design; and performing logic optimization on said design, said steps of placing, providing and performing logic optimization are performed concurrently for at least a portion of time, wherein one of said steps of placing, providing and performing logic optimization is performed on one portion of said design while another of said steps of placing, providing and performing logic optimization is performed on another portion of said design.
Claim 15
Dependent Claim
114 words
A processor readable storage device having processor readable code embodied on said processor readable storage device, said processor readable code for programming one or more processors to perform a method comprising the steps of: placing circuit elements of a design; providing routing or routing estimates for said design; and performing logic optimization on said design, said steps of placing, providing and performing logic optimization are performed concurrently for at least a portion of time, wherein one of said steps of placing, providing and performing logic optimization is performed on one portion of said design while another of said steps of placing, providing and performing logic optimization is performed on another portion of said design.
Claim 16
Dependent Claim
43 words
A processor readable storage device according to claim 13 , wherein said method further comprises the step of: performing a timing analysis on said design concurrently, for at least a portion of time, with said steps of placing, providing and performing logic optimization.
Claim 17
Dependent Claim
43 words
A processor readable storage device according to claim 13 , wherein said method further comprises the step of: performing a power analysis on said design concurrently, for at least a portion of time, with said steps of placing, providing and performing logic optimization.
Claim 18
Dependent Claim
47 words
A processor readable storage device according to claim 13 , wherein said method further comprises the step of: performing a timing analysis and a power analysis on said design concurrently, for at least a portion of time, with said steps of placing, providing and performing logic optimization.
Claim 19
Dependent Claim
25 words
A processor readable storage device according to claim 13 , wherein: said steps of placing, providing and performing logic optimization are performed by parallel processors.
Claim 20
Dependent Claim
61 words
A processor readable storage device according to claim 13 , wherein: said step of placing is performed on a first cluster of elements of said design while said step of providing is performed on a second cluster of elements of said design and while said step of performing logic optimization is performed on a third cluster of elements of said design.
Claim 21
Dependent Claim
100 words
A processor readable storage device according to claim 13 , wherein said method further comprises the steps of: dividing elements of said design into clusters; performing an initial placement and routing estimation of said design prior to said steps of placing, providing and performing logic optimization; and performing an inner loop and an outer loop, said inner loop includes performing said steps of placing, providing and performing logic optimization on a current set of clusters, said outer loop includes reducing cluster size and performing said inner loop on said reduced clusters until said cluster size is at a predefined level.
Claim 22
Independent Claim
115 words
An apparatus for performing design optimization, comprising: a processor readable device; and one or more processors in communication with said processor readable device, said one or more processor perform a method comprising the steps of: placing circuit elements of a design, providing routing or routing estimates for said design, and performing logic optimization on said design, said steps of placing, providing and performing logic optimization are performed concurrently for at least a portion of time, wherein one of said steps of placing, providing and performing logic optimization is performed on one portion of said design while another of said steps of placing, providing and performing logic optimization is performed on another portion of said design.
Claim 23
Independent Claim
115 words
An apparatus for performing design optimization, comprising: a processor readable device; and one or more processors in communication with said processor readable device, said one or more processor perform a method comprising the steps of: placing circuit elements of a design, providing routing or routing estimates for said design, and performing logic optimization on said design, said steps of placing, providing and performing logic optimization are performed concurrently for at least a portion of time, wherein one of said steps of placing, providing and performing logic optimization is performed on one portion of said design while another of said steps of placing, providing and performing logic optimization is performed on another portion of said design.
Claim 24
Dependent Claim
20 words
An apparatus according to claim 20 , wherein: said one or more processors include parallel processors for performing said method.
Claim 25
Dependent Claim
46 words
An apparatus according to claim 21 , wherein: said step of placing is performed by a first parallel processor while said step of providing is performed by a second parallel processor and while said step of performing logic optimization is performed by a third parallel processor.
Claim 26
Dependent Claim
73 words
An apparatus according to claim 21 , wherein: said step of placing is performed on a first set of one or more clusters of elements of said design while said step of providing is performed on a second set of one or more clusters of elements of said design and while said step of performing logic optimization is performed on a third set of one or more clusters of elements of said design.
Claim 27
Dependent Claim
41 words
An apparatus according to claim 21 , wherein said method further comprises: performing a timing analysis and a power analysis on said design concurrently, for at least a portion of time, with said steps of placing, providing and performing logic optimization.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-28 | 2006-10-28 | 2007-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-28 | 2010-10-28 | 2011-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-28 | 2014-10-28 | 2015-04-29 | $7700.00 | Window Closed / Lapsed |