Design hierarchy-based placement

Claim 1

A method for determining placement of a circuit within a substrate area of an integrated circuit chip, wherein the circuit is defined as comprising a plurality of logic modules, each logic module including a plurality of cells, the circuit being further defined as comprising connections for carrying signals between said cells, the method comprising the steps of: a. generating a trial placement by initially assigning each cell of said circuit to a position within the substrate area in a manner that is biased towards clustering cells of the same logic module while satisfying other positioning criteria; b. identifying a plurality of module core areas within the substrate area, each module core area corresponding to a separate one of the logic modules and encompassing assigned positions of cells of the corresponding logic module; c. defining a plurality of rectangular guiding blocks, each guiding block corresponding to a separate one of the module core areas and being sized relative to its corresponding module core area; d. assigning each guiding block to a position within said substrate area; and e. generating a second placement by reassigning each cell of said circuit to a position within the substrate area in a manner that is biased towards positioning cells of each logic module in a vicinity of the guiding block corresponding to the logic module while satisfying said other positioning criteria.

Claim 2

A method for determining placement of a circuit within a substrate area of an integrated circuit chip, wherein the circuit is defined as comprising a plurality of logic modules, each logic module including a plurality of cells, the circuit being further defined as comprising connections for carrying signals between said cells, the method comprising the steps of: a. generating a trial placement by initially assigning each cell of said circuit to a position within the substrate area in a manner that is biased towards clustering cells of the same logic module while satisfying other positioning criteria; b. identifying a plurality of module core areas within the substrate area, each module core area corresponding to a separate one of the logic modules and encompassing assigned positions of cells of the corresponding logic module; c. defining a plurality of rectangular guiding blocks, each guiding block corresponding to a separate one of the module core areas and being sized relative to its corresponding module core area; d. assigning each guiding block to a position within said substrate area; and e. generating a second placement by reassigning each cell of said circuit to a position within the substrate area in a manner that is biased towards positioning cells of each logic module in a vicinity of the guiding block corresponding to the logic module while satisfying said other positioning criteria.

Claim 14

A method for determining placement of a circuit within a substrate area of an integrated circuit chip, wherein the circuit is defined as comprising a plurality of logic modules, each logic module including a plurality of cells, the circuit being further defined as comprising connections for carrying signals between said cells, the method comprising the steps of: a. partitioning the substrate area into N first partitions wherein N is an integer greater than 1 ; b. identifying the cells included in each logic module and initially assigning the cells to positions within said first partitions such that at most N- 1 of said plurality of logic modules are divided, wherein cells of a divided module are assigned to more than one of said first partitions, and such that all others of said logic modules are undivided, wherein all cells of an undivided logic module are assigned to only one of said first partitions; and c. reassigning at least one of said cells of the divided module to a new position within said substrate area so as to satisfy a placement criterion.

Claim 15

A method for determining placement of a circuit within a substrate area of an integrated circuit chip, wherein the circuit is defined as comprising a plurality of logic modules, each logic module including a plurality of cells, the circuit being further defined as comprising connections for carrying signals between said cells, the method comprising the steps of: a. partitioning the substrate area into N first partitions wherein N is an integer greater than 1 ; b. identifying the cells included in each logic module and initially assigning the cells to positions within said first partitions such that at most N- 1 of said plurality of logic modules are divided, wherein cells of a divided module are assigned to more than one of said first partitions, and such that all others of said logic modules are undivided, wherein all cells of an undivided logic module are assigned to only one of said first partitions; and c. reassigning at least one of said cells of the divided module to a new position within said substrate area so as to satisfy a placement criterion.