Patent US6549041B2 successfully refreshed from Google Patents.
US6549041B2
Expired / Lapsed
US
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Scheme for delay locked loop reset protection
Assignee: Micron Technology Inc
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Filing: 2002-07-30
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Granted: 2003-04-15
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Expires: 2022-07-30
Abstract
Abstract Systems and methods are provided for operating a delay locked loop during a reset. The systems and methods provide for activating a reset mode signal to prevent a phase lock signal from forcing the DLL out of a reset, and deactivating the reset mode signal only after at least one shifting operation is performed to allow the phase lock signal to correctly allow the DLL to be out of the reset.
Inventors
- 👤 William C. Waldrop
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:20
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/10; H03L2207/00; H03L2207/14; H03L7/085; H03L7/095
Claims Analysis
Total Claims: 51
Claim 1
Independent Claim
106 words
A circuit comprising: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for disabling the shifting operation when the external and internal signals are synchronized; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
Claim 2
Dependent Claim
106 words
A circuit comprising: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for disabling the shifting operation when the external and internal signals are synchronized; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
Claim 3
Dependent Claim
92 words
The circuit of claim 1 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not performed in the reset mode; and an output logic connected to the flip flop for enabling the compare unit to disable the shifting operation when the external and internal signals are synchronized after the shift register is reset and after the shifting operation is performed.
Claim 4
Dependent Claim
105 words
A circuit comprising: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for determining a delay between the external and internal signals; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
Claim 5
Dependent Claim
105 words
A circuit comprising: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for determining a delay between the external and internal signals; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
Claim 6
Dependent Claim
76 words
The circuit of claim 3 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected during the reset mode; and an output logic connected to the flip flop for releasing the reset mode when the shifting operation is detected in the reset mode.
Claim 7
Dependent Claim
136 words
A circuit comprising: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate; a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; and a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
Claim 8
Dependent Claim
136 words
A circuit comprising: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate; a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; and a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
Claim 9
Dependent Claim
94 words
The circuit of claim 5 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected during the reset mode; and an output logic connected to the flip flop for releasing the reset mode to enable the reset unit to change the sampling after the shifting operation is detected during the reset mode and after the external and internal signals are synchronized.
Claim 10
Dependent Claim
18 words
The circuit of claim 5 , wherein the second sampling rate is slower than the first sampling rate.
Claim 11
Dependent Claim
21 words
The circuit of claim 5 , wherein the second sampling rate is about ten time slower than the first sampling rate.
Claim 12
Dependent Claim
147 words
An integrated circuit comprising: a plurality of memory cells; an output circuit for receiving data from the memory cells; and a delay circuit for providing timing to the output circuit to output the data to a plurality of data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for disabling the shifting operation when the external and internal signals are synchronized; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
Claim 13
Dependent Claim
147 words
An integrated circuit comprising: a plurality of memory cells; an output circuit for receiving data from the memory cells; and a delay circuit for providing timing to the output circuit to output the data to a plurality of data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for disabling the shifting operation when the external and internal signals are synchronized; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
Claim 14
Dependent Claim
93 words
The integrated circuit of claim 9 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected in the reset mode; and an output logic connected to the flip flop for enabling the compare unit to disable the shifting operation when the external and internal signals are synchronized after the shift register is reset and after the shifting operation is performed.
Claim 15
Dependent Claim
146 words
An integrated circuit comprising: a plurality of memory cells; an output circuit for receiving data from the memory cells; and a delay circuit for providing timing to the output circuit to output the data to a plurality of data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for determining a delay between the external and internal signals; a reset unit for resetting the shift register during a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
Claim 16
Dependent Claim
146 words
An integrated circuit comprising: a plurality of memory cells; an output circuit for receiving data from the memory cells; and a delay circuit for providing timing to the output circuit to output the data to a plurality of data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for determining a delay between the external and internal signals; a reset unit for resetting the shift register during a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
Claim 17
Dependent Claim
77 words
The integrated circuit of claim 11 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected during the reset mode; and an output logic connected to the flip flop for releasing the reset mode when the shifting operation is detected in the reset mode.
Claim 18
Dependent Claim
177 words
An integrated circuit comprising: a plurality of memory cells; an output circuit for receiving data from the memory cells; and a delay circuit for providing timing to the output circuit to output the data to a plurality of data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate; a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; and a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
Claim 19
Dependent Claim
177 words
An integrated circuit comprising: a plurality of memory cells; an output circuit for receiving data from the memory cells; and a delay circuit for providing timing to the output circuit to output the data to a plurality of data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate; a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; and a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
Claim 20
Dependent Claim
95 words
The integrated circuit of claim 13 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected during the reset mode; and an output logic connected to the flip flop for releasing the reset mode to enable the reset unit to change the sampling after the shifting operation is detected during the reset mode and after the external and internal signals are synchronized.
Claim 21
Dependent Claim
19 words
The integrated circuit of claim 13 , wherein the second sampling rate is slower than the first sampling rate.
Claim 22
Independent Claim
164 words
A system comprising: a processor; and a dynamic memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for disabling the shifting operation when the external and internal signals are synchronized; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
Claim 23
Independent Claim
164 words
A system comprising: a processor; and a dynamic memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for disabling the shifting operation when the external and internal signals are synchronized; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
Claim 24
Dependent Claim
92 words
The system of claim 16 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected in the reset mode; and an output logic connected to the flip flop for enabling the compare unit to disable the shifting operation when the external and internal signals are synchronized after the shift register is reset and after the shifting operation is performed.
Claim 25
Independent Claim
164 words
A system comprising: a processor; and a static memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for disabling the shifting operation when the external and internal signals are synchronized; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
Claim 26
Independent Claim
164 words
A system comprising: a processor; and a static memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for disabling the shifting operation when the external and internal signals are synchronized; a reset unit for resetting the shift register in a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
Claim 27
Dependent Claim
92 words
The system of claim 18 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected in the reset mode; and an output logic connected to the flip flop for enabling the compare unit to disable the shifting operation when the external and internal signals are synchronized after the shift register is reset and after the shifting operation is performed.
Claim 28
Independent Claim
163 words
A system comprising: a processor; and a dynamic memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for determining a delay between the external and internal signals; a reset unit for resetting the shift register during a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
Claim 29
Independent Claim
163 words
A system comprising: a processor; and a dynamic memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for determining a delay between the external and internal signals; a reset unit for resetting the shift register during a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
Claim 30
Dependent Claim
76 words
The system of claim 20 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected during the reset mode; and an output logic connected to the flip flop for releasing the reset mode when the shifting operation is detected in the reset mode.
Claim 31
Independent Claim
163 words
A system comprising: a processor; and a static memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for determining a delay between the external and internal signals; a reset unit for resetting the shift register during a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
Claim 32
Independent Claim
163 words
A system comprising: a processor; and a static memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for determining a delay between the external and internal signals; a reset unit for resetting the shift register during a reset mode; and a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
Claim 33
Dependent Claim
76 words
The system of claim 22 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected during the reset mode; and an output logic connected to the flip flop for releasing the reset mode when the shifting operation is detected in the reset mode.
Claim 34
Independent Claim
194 words
A system comprising: a processor; and a dynamic memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate; a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; and a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
Claim 35
Independent Claim
194 words
A system comprising: a processor; and a dynamic memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate; a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; and a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
Claim 36
Dependent Claim
94 words
The system of claim 24 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected during the reset mode; and an output logic connected to the flip flop for releasing the reset mode to enable the reset unit to change the sampling after the shifting operation is detected during the reset mode and after the external and internal signals are synchronized.
Claim 37
Independent Claim
194 words
A system comprising: a processor; and a static memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate; a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; and a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
Claim 38
Independent Claim
194 words
A system comprising: a processor; and a static memory device connected to the processor via a plurality of data lines, the memory device including: a plurality of memory cells; an output circuit for receiving data from the memory cells; a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including: a delay line for receiving an external signal to generate an internal signal; a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals; and a phase detector connected to the shift register, the phase detector including: a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate; a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; and a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
Claim 39
Dependent Claim
94 words
The system of claim 26 , wherein the false clock protection unit includes: an input logic for detecting an occurrence of the shifting operation; a flip flop connected to the input logic for holding the phase detector in the reset mode when the shifting operation is not detected during the reset mode; and an output logic connected to the flip flop for releasing the reset mode to enable the reset unit to change the sampling after the shifting operation is detected during the reset mode and after the external and internal signals are synchronized.
Claim 40
Independent Claim
59 words
A method comprising: delaying an external signal to generate an internal signal; determining a delay between the external and internal signals; performing a shifting operation to adjust the delay; disabling the shifting operation when the external and internal signals are synchronized; activating a reset signal in a reset mode; performing at least one shifting operation in the reset mode.
Claim 41
Independent Claim
59 words
A method comprising: delaying an external signal to generate an internal signal; determining a delay between the external and internal signals; performing a shifting operation to adjust the delay; disabling the shifting operation when the external and internal signals are synchronized; activating a reset signal in a reset mode; performing at least one shifting operation in the reset mode.
Claim 42
Dependent Claim
22 words
The method of claim 28 , determining a delay includes comparing the external signal and a delayed version of the internal signal.
Claim 43
Dependent Claim
58 words
The method of claim 28 , performing at least one shifting operation includes: detecting an occurrence of the shifting operation; holding a reset mode when the shifting operation is not performed in the reset mode; and disabling the shifting operation when the external and internal signals are synchronized after the shifting operation is performed in the reset mode.
Claim 44
Independent Claim
61 words
A method comprising: delaying an external signal to generate an internal signal; determining a delay between the external and internal signals; performing a shifting operation to adjust the delay; disabling the shifting operation when the external and internal signals are synchronized; activating a reset signal in a rest mode; and preventing the disabling of the shifting operation in the reset mode.
Claim 45
Independent Claim
61 words
A method comprising: delaying an external signal to generate an internal signal; determining a delay between the external and internal signals; performing a shifting operation to adjust the delay; disabling the shifting operation when the external and internal signals are synchronized; activating a reset signal in a rest mode; and preventing the disabling of the shifting operation in the reset mode.
Claim 46
Dependent Claim
23 words
The method of claim 31 , wherein determining a delay includes comparing the external signal and a delayed version of the internal signal.
Claim 47
Dependent Claim
48 words
The method of claim 31 , wherein preventing the disabling includes: detecting an occurrence of the shifting operation; holding the reset mode when the shifting operation is not performed in the reset mode; and releasing the reset mode when the shifting operation is detected in the reset mode.
Claim 48
Independent Claim
93 words
A method of comprising: delaying an external signal to generate an internal signal; comparing the external and internal signals based on a first sampling rate; performing a shifting operation based on the comparison to synchronize the external and internal signals; changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; activating a reset signal in a reset mode; and preventing the changing of the first sampling rate to the second sampling rate when the external and internal signals are not synchronized in the reset mode.
Claim 49
Independent Claim
93 words
A method of comprising: delaying an external signal to generate an internal signal; comparing the external and internal signals based on a first sampling rate; performing a shifting operation based on the comparison to synchronize the external and internal signals; changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized; activating a reset signal in a reset mode; and preventing the changing of the first sampling rate to the second sampling rate when the external and internal signals are not synchronized in the reset mode.
Claim 50
Dependent Claim
31 words
The method of claim 34 , wherein changing the first sampling rate to a second sampling rate includes selecting the second sampling rate to be slower than the first sampling rate.
Claim 51
Dependent Claim
59 words
The method of claim 34 , wherein preventing includes: detecting an occurrence of the shifting operation; holding the reset mode when the shifting operation is not performed in the reset mode; and releasing the reset mode; and changing the sampling after the shifting operation is detected during the reset mode and after the external and internal signals are synchronized.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
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|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-14 | 2006-10-14 | 2007-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-14 | 2010-10-14 | 2011-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-14 | 2014-10-14 | 2015-04-15 | $7700.00 | Window Closed / Lapsed |