Patent US6544822B2 successfully refreshed from Google Patents.
US6544822B2
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Method for fabricating MOSFET device
Assignee: SK Hynix Inc
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Filing: 2001-06-20
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Granted: 2003-04-08
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Expires: 2021-06-20
Abstract
Abstract A method for fabricating a MOSFET device having a metal gate with an ultra shallow junction and allowing the application of a self-aligned contact. A sacrificial gate is formed on a silicon substrate, as is a first silicon epitaxial layer, which is thinner than the sacrificial gate. Elevated source/drain regions are formed on the silicon substrate by implanting desired impurity ions. An interlayer insulating film is deposited over the resultant structure and polished to expose the sacrificial gate. A groove is formed in which a gate insulating film and a metal film are deposited. The metal film, the gate insulating film and the interlayer insulating film are polished until the first silicon epitaxial layer is exposed. A second silicon epitaxial layer is then formed on the first silicon epitaxial layer.
Inventors
- 👤 Tae Kyun Kim
- 👤 Dae Hee Weon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:47
CPC Classifications
H; H10; H10P; H10P10/00; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D64/017; H10W20/0698
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
174 words
A method for fabricating a MOSFET device, comprising: forming a sacrificial gate on an active region of a silicon substrate; forming a first silicon epitaxial layer, thinner than the sacrificial gate, on the silicon substrate at opposite sides of the sacrificial gate to cover the active region; forming elevated source/drain regions on the silicon substrate, respectively arranged at opposite sides of the sacrificial gate by implanting desired impurity ions into the silicon substrate via the first silicon epitaxial layer; forming an interlayer insulating film on the resultant structure; polishing the interlayer insulating film to expose the sacrificial gate; removing the exposed sacrificial gate to form a groove defining a region where a metal gate is to be formed; forming a gate insulating film and a metal film on the resultant structure sequentially; forming a metal gate within the groove by polishing the metal film, the gate insulating film and the interlayer insulating film until the first silicon epitaxial layer is exposed; and forming a second silicon epitaxial layer on the first silicon epitaxial layer.
Claim 2
Independent Claim
174 words
A method for fabricating a MOSFET device, comprising: forming a sacrificial gate on an active region of a silicon substrate; forming a first silicon epitaxial layer, thinner than the sacrificial gate, on the silicon substrate at opposite sides of the sacrificial gate to cover the active region; forming elevated source/drain regions on the silicon substrate, respectively arranged at opposite sides of the sacrificial gate by implanting desired impurity ions into the silicon substrate via the first silicon epitaxial layer; forming an interlayer insulating film on the resultant structure; polishing the interlayer insulating film to expose the sacrificial gate; removing the exposed sacrificial gate to form a groove defining a region where a metal gate is to be formed; forming a gate insulating film and a metal film on the resultant structure sequentially; forming a metal gate within the groove by polishing the metal film, the gate insulating film and the interlayer insulating film until the first silicon epitaxial layer is exposed; and forming a second silicon epitaxial layer on the first silicon epitaxial layer.
Claim 3
Dependent Claim
42 words
The method according to claim 1 , wherein the first and the second silicon epitaxial layers are formed in accordance with a selective epitaxial growth process using a UHV-CVD (ultrahigh vacuum-chemical vapor deposition) method or a LP-CVD (low pressure-chemical vapor deposition) method.
Claim 4
Dependent Claim
44 words
The method according to claim 2 , wherein the selective epitaxial growth process using the UHV-CVD method is conducted using Si 2 H 6 gas and Cl 2 gas at a pressure of several mTorr and at the temperature of 400 to 800° C.
Claim 5
Dependent Claim
59 words
The method according to claim 2 , wherein the selective epitaxial growth process using the LP-CVD method is conducted using H 2 gas as a carrier gas, DCS (dichloral silane) and HCl gas of hundreds of sccm as a deposition gas at a pressure of several to hundreds of Torr and at a temperature of 750 to 1,000° C.
Claim 6
Dependent Claim
34 words
The method according to claim 2 , wherein the selective epitaxial growth process includes an additional hydrogen bake process carried out at a temperature of 800 to 1,000° C. for 1 to 3 minutes.
Claim 7
Dependent Claim
26 words
The method according to claim 4 , wherein the selective epitaxial growth process is conducted to grow silicon germanium epitaxial layer by adding GeH 4 gas.
Claim 8
Dependent Claim
32 words
The method according to claim 2 , wherein PH 3 or AsH 3 gas is doped in an in-situ fashion during the selective epitaxial growth to form the first silicon epitaxial layer.
Claim 9
Dependent Claim
36 words
The method according to claim 7 , wherein the flow rate of the PH 3 or the AsH 3 gas is hundreds of sccm and the concentration is 1×10 19 to 10 20 ions/cm 2 .
Claim 10
Dependent Claim
23 words
The method according to claim 1 , wherein the first silicon epitaxial layer is formed to a thickness of 1,500 to 3,000 Å.
Claim 11
Dependent Claim
23 words
The method according to claim 1 , wherein the second silicon epitaxial layer is formed to a thickness of 400 to 700 Å.
References Cited (Backward Citations)
US6232641B1
Cited
US6277677B1
Cited
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