US6538957B2
Expired / Lapsed
US
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Apparatus and method for distributing a clock signal on a large scale integrated circuit
Assignee: Sony Interactive Entertainment Inc
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Filing: 2001-08-14
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Granted: 2003-03-25
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Expires: 2021-08-14
Abstract
Abstract A semiconductor chip includes a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers, each including a delay lock loop (DLL) circuit providing a DDL function and each being operable to produce a respective output clock signal from an associated input clock signal in accordance with the DLL function, the outputs of an Nth level subset of the plurality of clock buffers being coupled to respective ones of the plurality of regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the output clock signals of at least two of the regional clock distribution nodes, wherein the DDL circuits of the Nth subset of clock buffers adjust the respective output clock signals in accordance with the respective error signals such that the output clock signals of the regional clock distribution nodes are substantially coincident.
Inventors
- 👤 Hidetaka Magoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:42
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
153 words
A semiconductor chip, comprising: a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers, each including a delay lock loop (DLL) circuit providing a DLL function and each being operable to produce a respective output clock signal from an associated input clock signal in accordance with the DLL function, the outputs of a subset of the plurality of clock buffers being coupled to respective ones of the plurality of regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the output clock signals of at least two of the regional clock distribution nodes, wherein the DLL circuits of the Nth subset of clock buffers adjust the respective output clock signals in accordance with the respective error signals such that the output clock signals of the regional clock distribution nodes are substantially coincident.
Claim 2
Dependent Claim
153 words
A semiconductor chip, comprising: a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers, each including a delay lock loop (DLL) circuit providing a DLL function and each being operable to produce a respective output clock signal from an associated input clock signal in accordance with the DLL function, the outputs of a subset of the plurality of clock buffers being coupled to respective ones of the plurality of regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the output clock signals of at least two of the regional clock distribution nodes, wherein the DLL circuits of the Nth subset of clock buffers adjust the respective output clock signals in accordance with the respective error signals such that the output clock signals of the regional clock distribution nodes are substantially coincident.
Claim 3
Dependent Claim
33 words
The semiconductor chip of claim 1 , wherein the clock buffers are coupled to one another to form a clock distribution tree from a global clock source to the regional clock distribution nodes.
Claim 4
Dependent Claim
15 words
The semiconductor chip of claim 2 , wherein the clock distribution tree is an H-tree.
Claim 5
Dependent Claim
26 words
The semiconductor chip of claim 2 , wherein first through Nth level subsets of the plurality of clock buffers define distribution levels of the distribution tree.
Claim 6
Dependent Claim
50 words
The semiconductor chip of claim 4 , wherein the respective clock buffers of the first level subset are operable to produce respective first level output clock signals from a global source clock signal of the global clock source in accordance with their DLL functions and one of the error signals.
Claim 7
Dependent Claim
40 words
The semiconductor chip of claim 5 , wherein the one error signal is provided by one of the plurality of phase detectors that monitors a phase difference between the output clock signals of two of the regional clock distribution nodes.
Claim 8
Dependent Claim
45 words
The semiconductor chip of claim 5 , wherein respective groups of clock buffers of a second level subset are operable to produce respective second level output clock signals from the respective first level clock signals in accordance with their DLL functions and respective error signals.
Claim 9
Dependent Claim
37 words
The semiconductor chip of claim 7 , wherein the respective error signals are provided by respective phase detectors that monitor respective phase differences between the output clock signals of respective pairs of the regional clock distribution nodes.
Claim 10
Dependent Claim
45 words
The semiconductor chip of claim 7 , wherein respective groups of clock buffers of a third level subset are operable to produce respective third level output clock signals from the respective second level clock signals in accordance with their DLL functions and respective error signals.
Claim 11
Dependent Claim
37 words
The semiconductor chip of claim 9 , wherein the respective error signals are provided by respective phase detectors that monitor respective phase differences between the output clock signals of respective pairs of the regional clock distribution nodes.
Claim 12
Dependent Claim
50 words
The semiconductor chip of claim 9 , wherein respective groups of clock buffers of a fourth level subset are operable to produce the output clock signals of the respective regional clock distribution nodes from the respective third level clock signals in accordance with their DLL functions and respective error signals.
Claim 13
Dependent Claim
37 words
The semiconductor chip of claim 11 , wherein the respective error signals are provided by respective phase detectors that monitor respective phase differences between the output clock signals of respective pairs of the regional clock distribution nodes.
Claim 14
Dependent Claim
82 words
The semiconductor chip of claim 1 , wherein: the semiconductor chip includes a global operative area defined by a plurality of regional areas, at least one sub-regional area within each regional area, and at least one local area within each sub-regional area; and at least one of the regional clock distribution nodes is disposed in each of the regional areas such that the respective outputs of the subset of clock buffers provides a regional clock signal to each of the regional areas.
Claim 15
Dependent Claim
70 words
The semiconductor chip of claim 13 , further comprising: a plurality of sub-regional clock distribution nodes, at least one sub-regional clock distribution node being disposed in each sub-regional area; and a plurality of RC-balanced clock signal paths coupled from each regional clock distribution node to the respective sub-regional clock distribution nodes of the respective regional areas such that respective sub-regional clock signals are provided at each sub-regional clock distribution node.
Claim 16
Dependent Claim
122 words
The semiconductor chip of claim 14 , further comprising: a plurality of local clock distribution nodes arranged in respective distribution grids, at least one of the distribution grids being disposed in each local area; and a plurality of local clock buffers, respective ones of the local clock buffers receiving an associated one of the sub-regional clock signals from one of the sub-regional clock distribution nodes and producing a local clock signal on a respective one of the distribution grids, each local clock buffer including at least part of an active feedback function operable to cause the local clock signal at one of the local clock distribution nodes of the respective distribution grid to be substantially coincident with the associated sub-regional clock signal.
Claim 17
Dependent Claim
101 words
The semiconductor chip of claim 15 , wherein: each local clock buffer includes a delay lock loop (DLL) circuit providing a DLL function and is operable to produce a respective one of the local clock signals from the associated sub-regional clock signal in accordance with the DLL function and an associated error signal; and the semiconductor chip further comprises a plurality of local phase detectors, each being operable to produce a respective one of the error signals based on phase differences between the local clock signal at the one of the local clock distribution nodes and the associated sub-regional clock signal.
Claim 18
Dependent Claim
43 words
The semiconductor chip of claim 15 , further comprising a phase lock loop operable to adjust a phase of the global source clock signal such that a phase difference between a system clock signal and one of the local clock signals is minimized.
Claim 19
Dependent Claim
35 words
The semiconductor chip of claim 17 , wherein the one of the local clock signals is taken from one of the local clock distribution nodes that is substantially distant from the associated local clock buffer.
Claim 20
Dependent Claim
136 words
A semiconductor chip, comprising: a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers grouped into i-th levels, where i=1, 2 . . . N, each clock buffer being operable to output a respective i-th level clock signal from an associated (i−1)th level clock signal in accordance with a delay lock loop (DLL) function, where the respective Nth level clock signals are coupled to the regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the i-th level clock signals of respective pairs of the regional clock distribution nodes, wherein the i-th level clock buffers adjust transitions of the respective i-th level clock signals in accordance with the DLL functions and the respective error signals.
Claim 21
Dependent Claim
136 words
A semiconductor chip, comprising: a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers grouped into i-th levels, where i=1, 2 . . . N, each clock buffer being operable to output a respective i-th level clock signal from an associated (i−1)th level clock signal in accordance with a delay lock loop (DLL) function, where the respective Nth level clock signals are coupled to the regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the i-th level clock signals of respective pairs of the regional clock distribution nodes, wherein the i-th level clock buffers adjust transitions of the respective i-th level clock signals in accordance with the DLL functions and the respective error signals.
Claim 22
Dependent Claim
80 words
The semiconductor chip of claim 19 , wherein: the semiconductor chip includes a global operative area defined by a plurality of regional areas, at least one sub-regional area within each regional area, and at least one local area within each sub-regional area; and at least one of the regional clock distribution nodes is disposed in each of the regional areas such that each Nth level clock signal provides a regional clock signal to a respective one of the regional areas.
Claim 23
Dependent Claim
70 words
The semiconductor chip of claim 20 , further comprising: a plurality of sub-regional clock distribution nodes, at least one sub-regional clock distribution node being disposed in each sub-regional area; and a plurality of RC-balanced clock signal paths coupled from each regional clock distribution node to the respective sub-regional clock distribution nodes of the respective regional areas such that respective sub-regional clock signals are provided at each sub-regional clock distribution node.
Claim 24
Dependent Claim
122 words
The semiconductor chip of claim 21 , further comprising: a plurality of local clock distribution nodes arranged in respective distribution grids, at least one of the distribution grids being disposed in each local area; and a plurality of local clock buffers, respective ones of the local clock buffers receiving an associated one of the sub-regional clock signals from one of the sub-regional clock distribution nodes and producing a local clock signal on a respective one of the distribution grids, each local clock buffer including at least part of an active feedback function operable to cause the local clock signal at one of the local clock distribution nodes of the respective distribution grid to be substantially coincident with the associated sub-regional clock signal.
Claim 25
Dependent Claim
101 words
The semiconductor chip of claim 22 , wherein: each local clock buffer includes a delay lock loop (DLL) circuit providing a DLL function and is operable to produce a respective one of the local clock signals from the associated sub-regional clock signal in accordance with the DLL function and an associated error signal; and the semiconductor chip further comprises a plurality of local phase detectors, each being operable to produce a respective one of the error signals based on phase differences between the local clock signal at the one of the local clock distribution nodes and the associated sub-regional clock signal.
Claim 26
Dependent Claim
43 words
The semiconductor chip of claim 22 , further comprising a phase lock loop operable to adjust a phase of the global source clock signal such that a phase difference between a system clock signal and one of the local clock signals is minimized.
Claim 27
Dependent Claim
35 words
The semiconductor chip of claim 24 , wherein the one of the local clock signals is taken from one of the local clock distribution nodes that is substantially distant from the associated local clock buffer.
Claim 28
Independent Claim
124 words
A method of distributing clock signals to areas of a semiconductor chip, comprising: receiving a clock source signal, where the clock source signal is a 0−th level clock signal; producing respective i-th level clock signals from associated (i−1)th level clock signals, where i=1, 2, . . . N; distributing the Nth level clock signals to respective regional clock distribution nodes located in regional areas of the semiconductor chip; producing respective error signals indicative of phase differences between respective pairs of the Nth level clock signals of the regional clock distribution nodes; adjusting instances at which the i-th level clock signals transition in accordance with the respective error signals such that the Nth level clock signals of the regional clock distribution nodes are substantially coincident.
Claim 29
Independent Claim
124 words
A method of distributing clock signals to areas of a semiconductor chip, comprising: receiving a clock source signal, where the clock source signal is a 0−th level clock signal; producing respective i-th level clock signals from associated (i−1)th level clock signals, where i=1, 2, . . . N; distributing the Nth level clock signals to respective regional clock distribution nodes located in regional areas of the semiconductor chip; producing respective error signals indicative of phase differences between respective pairs of the Nth level clock signals of the regional clock distribution nodes; adjusting instances at which the i-th level clock signals transition in accordance with the respective error signals such that the Nth level clock signals of the regional clock distribution nodes are substantially coincident.
Claim 30
Dependent Claim
33 words
The method of claim 26 , wherein electrical paths from the global clock source signal to the Nth level output clock signals of the regional clock distribution nodes forms a clock distribution tree.
Claim 31
Dependent Claim
14 words
The method of claim 27 , wherein the clock distribution tree is an H-tree.
Claim 32
Dependent Claim
75 words
The method of claim 26 , further comprising dividing the semiconductor chip into a global operative area defined by a plurality of regional areas, at least one sub-regional area within each regional area, and at least one local area within each sub-regional area, wherein at least one of the regional clock distribution nodes is disposed in each of the regional areas such that a regional clock signal is provided to each of the regional areas.
Claim 33
Dependent Claim
61 words
The method of claim 26 , further comprising distributing the regional clock signals over a plurality of RC-balanced clock signal paths coupled from each regional clock distribution node to respective sub-regional clock distribution nodes, at least one sub-regional clock distribution node being disposed in each sub-regional area, such that respective sub-regional clock signals are provided at each sub-regional clock distribution node.
Claim 34
Dependent Claim
113 words
The method of claim 30 , further comprising: distributing the respective sub-regional clock signals over respective distribution grids, each coupled to a respective plurality of local clock distribution nodes, at least one of the distribution grids being disposed in each local area, such that respective local clock signals are provided at the respective pluralities of local clock distribution nodes; and adjusting instances at which the respective sub-regional clock signals transition in accordance with respective local DLL functions prior to distribution over the respective distribution grids such that the local clock signal at one of the local clock distribution nodes of the respective distribution grids is substantially coincident with the respective sub-regional clock signals.
Claim 35
Dependent Claim
36 words
The method of claim 31 , further comprising adjusting a phase of the global source clock signal such that a phase difference between a system clock signal and one of the local clock signals is minimized.
Claim 36
Independent Claim
223 words
A method of distributing clock signals to a plurality of regional clock distribution nodes located on a semiconductor chip using a plurality of clock buffers grouped into i-th levels, where i=1, 2 . . . N, each clock buffer being operable to output a respective i-th level clock signal from an associated (i−1)th level clock signal in accordance with a delay lock loop (DLL) function, where the respective Nth level clock signals are coupled to the regional clock distribution nodes, and using a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the clock signals of respective pairs of the regional clock distribution nodes, where the i-th level clock buffers adjust transitions of the respective i-th level clock signals in accordance with the DLL functions and the respective error signals, the method comprising: causing the respective i-th level clock buffers to neither substantially delay nor substantially advance the transitions of the respective i-th level clock signals; permitting the (N−j)th level clock buffers to adjust the transitions of the respective (N−i)th level clock signals, where j=0, 1, 2, . . . N−1; and repeating the previous step for each level such that the Nth level clock signals of the regional clock distribution nodes are substantially coincident with one another and a 0th level clock signal.
Claim 37
Independent Claim
223 words
A method of distributing clock signals to a plurality of regional clock distribution nodes located on a semiconductor chip using a plurality of clock buffers grouped into i-th levels, where i=1, 2 . . . N, each clock buffer being operable to output a respective i-th level clock signal from an associated (i−1)th level clock signal in accordance with a delay lock loop (DLL) function, where the respective Nth level clock signals are coupled to the regional clock distribution nodes, and using a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the clock signals of respective pairs of the regional clock distribution nodes, where the i-th level clock buffers adjust transitions of the respective i-th level clock signals in accordance with the DLL functions and the respective error signals, the method comprising: causing the respective i-th level clock buffers to neither substantially delay nor substantially advance the transitions of the respective i-th level clock signals; permitting the (N−j)th level clock buffers to adjust the transitions of the respective (N−i)th level clock signals, where j=0, 1, 2, . . . N−1; and repeating the previous step for each level such that the Nth level clock signals of the regional clock distribution nodes are substantially coincident with one another and a 0th level clock signal.
References Cited (Backward Citations)
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Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-03-24 | 2006-09-23 | 2007-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-24 | 2010-09-23 | 2011-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-24 | 2014-09-23 | 2015-03-25 | $7700.00 | Window Closed / Lapsed |