Patent US6537867B1 successfully refreshed from Google Patents.
US6537867B1
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US
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High speed low voltage semiconductor devices and method of fabrication
Assignee: Bell Semiconductor LLC
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Filing: 2000-08-02
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Granted: 2003-03-25
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Expires: 2020-08-02
Abstract
Abstract A digit signal processor capable of operating at 100 MHZ with a 1.0 volt power supply. The digital signal processor is fabricated by application of strong phase-shift lithography to obtain a 0.12 μm gate dimension. A dual-mask process is utilized to improve resolution thereby producing high speed, low-voltage processors. A n + /p + dual-Poly:Si module, and dopant penetration suppression techniques may be utilized.
Inventors
- 👤 Ronald L. Freyman
- 👤 Isik C. Kizilyalli
- 👤 Ross A. Kohler
- 👤 Omkaram Nalamasu
- 👤 Mark R. Pinto
- 👤 Joseph R. Radosevich
- 👤 Robert M. Vella
- 👤 George P. Watson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:38
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/71
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
88 words
A method of fabricating a semiconductor device component comprising: providing a substrate; providing a dielectric layer on the substrate; providing a component layer on the dielectric layer; providing a hard mask layer on top of the component layer; providing radiation-sensitive material on the hard mask layer; exposing the radiation-sensitive material to pattern the hard mask layer wherein exposures are made utilizing a multiple-mask exposure process; etching the hard mask layer to the component layer; removing the radiation-sensitive material; etching the component layer as patterned by the hard mask.
Claim 2
Independent Claim
88 words
A method of fabricating a semiconductor device component comprising: providing a substrate; providing a dielectric layer on the substrate; providing a component layer on the dielectric layer; providing a hard mask layer on top of the component layer; providing radiation-sensitive material on the hard mask layer; exposing the radiation-sensitive material to pattern the hard mask layer wherein exposures are made utilizing a multiple-mask exposure process; etching the hard mask layer to the component layer; removing the radiation-sensitive material; etching the component layer as patterned by the hard mask.
Claim 3
Dependent Claim
64 words
The method of claim 1 wherein the multiple-mask process comprises: exposing the radiation-sensitive material through a phase-shift mask to define a first portion of the component; and exposing the radiation-sensitive material through a non-phase-shift mask to shadow the first portion of the component and define a second portion of the component, wherein either the phase-shifting exposure or the non-phase-shifting exposure may be performed first.
Claim 4
Dependent Claim
24 words
The method of claim 2 wherein the first component portion is an active region and the second component portion is a field oxide region.
Claim 5
Dependent Claim
30 words
The method of claim 2 further comprising exposing the first component portion with an exposure dose in the range of about 20 mJ/cm 2 to about 40 mJ/cm 2 .
Claim 6
Dependent Claim
30 words
The method of claim 2 further comprising exposing the second component portion with an exposure dose in the range of about 20 mJ/cm 2 to about 40 mJ/cm 2 .
Claim 7
Dependent Claim
14 words
The method of claim 2 wherein the phase-shift mask is a dark field mask.
Claim 8
Dependent Claim
16 words
The method of claim 2 wherein the a non-phase-shift mask is a bright field binary mask.
Claim 9
Dependent Claim
23 words
The method of claim 2 wherein the phase-shift mask is selected from the group consisting of strong phase-shift mask and alternating aperture mask.
Claim 10
Dependent Claim
18 words
The method of claim 1 wherein the radiation-sensitive material is exposed with a 248 nm wavelength radiation source.
Claim 11
Dependent Claim
13 words
The method of claim 1 wherein the substrate is silicon or gallium arsenide.
Claim 12
Dependent Claim
36 words
The method of claim 1 wherein the dielectric layer is selected from the group consisting of SiO 2 , SiO 2 /Si 3 N 4 stack, Ta 2 O 5 , SiO 2 with incorporated nitrogen.
Claim 13
Dependent Claim
44 words
The method of claim 11 wherein the dielectric layer is formed by a method selected from SiO 2 growth followed by Si 3 N 4 deposition, N 2 introduction during SiO 2 growth, and N 2 implantation of substrate followed by SiO 2 growth.
Claim 14
Dependent Claim
36 words
The method of claim 1 wherein the component layer is selected from the group consisting of polysilicon, amorphous silicon, titanium nitride disposed on polysilicon, tungsten, tungsten silicide disposed on polysilicon, tantalum and tantalum disposed on polysilicide.
Claim 15
Dependent Claim
26 words
The method of claim 1 wherein the component layer is selected from the group consisting of aluminum, tungsten or a stack of Ti, TiN, Al, TiN.
Claim 16
Dependent Claim
27 words
The method of claim 1 wherein one or more dopants are introduced into at least a portion of the component layer to form an n + layer.
Claim 17
Dependent Claim
21 words
The method of claim 15 wherein the dopant is selected from the group consisting of arsenic, phosphorus and a combination thereof.
Claim 18
Dependent Claim
27 words
The method of claim 1 wherein one or more dopants are introduced into at least a portion of the component layer to form a p + layer.
Claim 19
Dependent Claim
24 words
The method of claim 17 wherein the p + dopant is selected from the group consisting of boron, BF 2 and a combination thereof.
Claim 20
Dependent Claim
25 words
The method of claim 1 wherein a p + dopant comprising boron and an n + dopant comprising phosphorus are introduced into the component layer.
Claim 21
Dependent Claim
27 words
The method of claim 1 wherein the hard mask layer is selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and spin on glass.
Claim 22
Dependent Claim
34 words
The method of claim 1 wherein the hard mask layer is provided on the component layer by a method selected from the group consisting of chemical vapor deposition and plasma enhanced chemical vapor deposition.
Claim 23
Dependent Claim
27 words
The method of claim 1 wherein the hard mask is etched by a method selected from the group consisting of reactive ion etching and anisotropic plasma etching.
Claim 24
Dependent Claim
39 words
The method of claim 1 wherein the hard mask is etched with an etchant selected from the group consisting of CHF 3 /CF 4 mixture, CHF 3 /CF 4 /Ar mixture, and CHF 3 /CF 4 /O 2 mixture.
Claim 25
Dependent Claim
27 words
The method of claim 1 wherein the component layer is etched by a method selected from the group consisting of reactive ion etching and anisotropic plasma etching.
Claim 26
Dependent Claim
43 words
The method of claim 1 wherein the component layer is etched with an etchant selected from the group consisting of Cl/HBr mixture, Cl/HBr/He mixture, Cl/HBr/O 2 mixture, CF 4 , SF 6 , and a chlorine mixture with or without N 2 .
Claim 27
Dependent Claim
34 words
The method of claim 1 wherein the component layer is provided on the dielectric layer by a method selected from the group consisting of chemical vapor deposition, physical vapor deposition and a combination thereof.
Claim 28
Dependent Claim
12 words
The method of claim 1 wherein the radiation-sensitive material is a photoresist.
Claim 29
Dependent Claim
13 words
The method of claim 1 wherein the device component is a gate electrode.
Claim 30
Dependent Claim
32 words
The method of claim 28 wherein the component layer is formed by: providing a semiconductor layer; providing a barrier layer on the semiconductor layer; providing a metal-containing layer on the barrier layer.
Claim 31
Dependent Claim
20 words
The method of claim 29 wherein the barrier layer is selected from a group consisting of WSiN, TaN and WN.
Claim 32
Dependent Claim
20 words
The method of claim 29 wherein the metal-containing layer is selected from a group consisting of WSi, TaSi and W.
Claim 33
Dependent Claim
13 words
The method of claim 1 wherein the device component is a gate electrode.
Claim 34
Dependent Claim
22 words
The method of claim 1 wherein the hard mask is patterned, at least in part, with an image representing random logic circuitry.
Claim 35
Dependent Claim
21 words
The method of claim 1 wherein the multi-mask exposure process provides a critical component dimension of less than about 0.12 μm.
Claim 36
Dependent Claim
24 words
The method of claim 1 wherein the multi-mask exposure process provides a frequency of greater than about 50 MHz for a digital signal processor.
Claim 37
Independent Claim
210 words
A method of fabricating a gate electrode useful in the manufacture of a digital signal processor, the method comprising: providing a silicon substrate; providing a SiO 2 layer on the substrate; providing a Si 3 N 4 layer on the SiO 2 layer; providing a polysilicon layer on the Si 3 N 4 layer; implanting phosphorus in the polysilicon layer to form an n + region; implanting boron in the polysilicon layer to form a p + region; depositing WSiN on the polysilicon layer; depositing WSi on the WSiN layer; providing a SiO 2 layer on top of the WSi layer; providing a photoresist layer on the SiO 2 layer; exposing the photoresist, with a 248 nm wavelength light source, through a dark field phase-shift mask to define a first portion of the gate electrode; exposing the photoresist, with a 248 nm laser, through a bright field binary mask to shadow the first portion of the gate electrode and define a second portion of the gate electrode, wherein either the phase-shifting exposure or the binary exposure may be performed first; etching the SiO 2 layer to the WSi; removing the photo resist; etching the WSi and WSiN with anisotropic plasma etch; and etching the polysilicon with an anisotropic plasma etch.
Claim 38
Independent Claim
210 words
A method of fabricating a gate electrode useful in the manufacture of a digital signal processor, the method comprising: providing a silicon substrate; providing a SiO 2 layer on the substrate; providing a Si 3 N 4 layer on the SiO 2 layer; providing a polysilicon layer on the Si 3 N 4 layer; implanting phosphorus in the polysilicon layer to form an n + region; implanting boron in the polysilicon layer to form a p + region; depositing WSiN on the polysilicon layer; depositing WSi on the WSiN layer; providing a SiO 2 layer on top of the WSi layer; providing a photoresist layer on the SiO 2 layer; exposing the photoresist, with a 248 nm wavelength light source, through a dark field phase-shift mask to define a first portion of the gate electrode; exposing the photoresist, with a 248 nm laser, through a bright field binary mask to shadow the first portion of the gate electrode and define a second portion of the gate electrode, wherein either the phase-shifting exposure or the binary exposure may be performed first; etching the SiO 2 layer to the WSi; removing the photo resist; etching the WSi and WSiN with anisotropic plasma etch; and etching the polysilicon with an anisotropic plasma etch.
Claim 39
Independent Claim
170 words
A method of fabricating a gate electrode useful in the manufacture of a digital signal processor, the method comprising: providing a substrate; providing a gate oxide layer on the substrate; providing a dielectric layer on the gate oxide layer; providing a gate electrode layer on the dielectric layer; forming an n + region in the gate electrode layer; forming a p + region in the gate electrode layer; providing a barrier layer on the gate electrode layer; providing a hard mask layer on the barrier layer; providing a photoresist layer on the hard mask layer; exposing the photoresist through a phase-shift mask to define a first portion of the gate electrode; exposing the photoresist through a non-phase-shift mask to shadow the first portion of the gate electrode and define a second portion of the gate electrode, wherein either the phase-shifting exposure or the non-phase-shift exposure may be performed first; etching the hard mask layer to the barrier layer; removing the photo resist; and etching the gate electrode and barrier layers.
Claim 40
Independent Claim
170 words
A method of fabricating a gate electrode useful in the manufacture of a digital signal processor, the method comprising: providing a substrate; providing a gate oxide layer on the substrate; providing a dielectric layer on the gate oxide layer; providing a gate electrode layer on the dielectric layer; forming an n + region in the gate electrode layer; forming a p + region in the gate electrode layer; providing a barrier layer on the gate electrode layer; providing a hard mask layer on the barrier layer; providing a photoresist layer on the hard mask layer; exposing the photoresist through a phase-shift mask to define a first portion of the gate electrode; exposing the photoresist through a non-phase-shift mask to shadow the first portion of the gate electrode and define a second portion of the gate electrode, wherein either the phase-shifting exposure or the non-phase-shift exposure may be performed first; etching the hard mask layer to the barrier layer; removing the photo resist; and etching the gate electrode and barrier layers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-24 | 2006-09-23 | 2007-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-24 | 2010-09-23 | 2011-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-24 | 2014-09-23 | 2015-03-25 | $7700.00 | Window Closed / Lapsed |