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US6531357B2
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Method of manufacturing a semiconductor device
Assignee: Kioxia Corp
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Filing: 2001-08-03
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Granted: 2003-03-11
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Expires: 2021-08-03
Abstract
Abstract A method of manufacturing a semiconductor memory device is described. The method includes forming isolations regions on a major surface of a semiconductor substrate with a width of an isolation region at an end portion of a memory cell array of the isolation regions becoming larger than width of an isolation region in an internal portion of the cell array of the isolation regions. Gate electrodes are formed on element regions surrounded by the isolation regions with a spacing between neighboring ones of the gate electrodes at the end portion of the memory cell array becoming larger than a spacing between neighboring ones of the gate electrodes in the internal portion of the memory cell array.
Inventors
- 👤 Yuji Takeuchi
- 👤 Fumitaka Arai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:17
CPC Classifications
H; H10; H10P; H10P76/00; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10B; H10B69/00; H10B41/00; H10B41/30; H10B41/35; H10B41/40; H10B41/41
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
114 words
A method of manufacturing a semiconductor memory device, comprising: forming isolation regions on a major surface of a semiconductor substrate with a width of an isolation region at an end portion of a memory cell array of the isolation regions becoming larger than a width of an isolation region in an internal portion of the memory cell array of the isolation regions; and forming gate electrodes on element regions surrounded by the isolation regions with a spacing between neighboring ones of the gate electrodes at the end portion of the memory cell array becoming larger than a spacing between neighboring ones of the gate electrodes in the internal portion of the memory cell array.
Claim 2
Independent Claim
114 words
A method of manufacturing a semiconductor memory device, comprising: forming isolation regions on a major surface of a semiconductor substrate with a width of an isolation region at an end portion of a memory cell array of the isolation regions becoming larger than a width of an isolation region in an internal portion of the memory cell array of the isolation regions; and forming gate electrodes on element regions surrounded by the isolation regions with a spacing between neighboring ones of the gate electrodes at the end portion of the memory cell array becoming larger than a spacing between neighboring ones of the gate electrodes in the internal portion of the memory cell array.
Claim 3
Dependent Claim
61 words
The method according to claim 1 , wherein the forming of the isolation regions includes forming the element regions with a width of an element region at the end portion of the memory cell array of the element regions becoming larger than a width of an element region in the internal portion of the memory cell array of the element regions.
Claim 4
Dependent Claim
48 words
The method according to claim 2 , wherein the forming of the isolation regions includes forming a width Ln of an n-th (n: a natural number) isolation region of the isolation regions from the end portion of the memory cell array toward the internal portion to satisfy Ln−1>Ln>Ln+1.
Claim 5
Dependent Claim
49 words
The method according to claim 1 , wherein the forming of the isolation regions includes forming a width Tn of an n-th (n: a natural number) element region of the isolation regions from the end portion of the memory cell array toward the internal portion to satisfy Tn−1>Tn >Tn+1.
Claim 6
Dependent Claim
56 words
The method according to claim 1 , wherein the forming of the gate electrodes includes forming a spacing Sn between an n-th (n: a natural number) gate electrode of the gate electrodes from the end portion of the memory cell array toward the internal portion and the neighboring ones of the gate electrodes to satisfy Sn−1>Sn>Sn+1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-10 | 2006-09-09 | 2007-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-10 | 2010-09-09 | 2011-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-10 | 2014-09-09 | 2015-03-11 | $7700.00 | Window Closed / Lapsed |