MOSFETs with differing gate dielectrics and method of formation

Claim 2

A semiconductor wafer comprising: a layer of semiconductor material; an NMOS device, the NMOS device including: a first source, a first drain and a first body formed from the layer of semiconductor material, the first body disposed between the first source and the first drain; and a first gate formed over the first body and having a first gate electrode defining a first channel interposed between the first source and the first drain, the first gate electrode is disposed on a high-K gate dielectric layer that extends continuously from the first gate electrode to the layer of semiconductor material; and a PMOS device, the PMOS device including: a second source, a second drain and a second body formed from the layer of semiconductor material, the second body disposed between the second source and the second drain; and a second gate formed over the second body and having a second gate electrode defining a second channel interposed between the second source and the second drain, the second gate electrode separated from the layer of semiconductor material by a standard-K gate dielectric.

Claim 3

The semiconductor wafer according to claim 1 , wherein the high-K gate dielectric has a relative permittivity of about twenty or higher.

Claim 4

The semiconductor wafer according to claim 1 , wherein the high-K gate dielectric is composed of one or more materials selected from hafnium oxide, zirconium oxide, cerium oxide, aluminum oxide, titanium oxide, yttrium oxide, barium strontium titanate and mixtures thereof.

Claim 5

The semiconductor wafer according to claim 1 , wherein the standard-K gate dielectric is composed of one or more materials selected from a nitride or an oxynitride.

Claim 6

The semiconductor wafer according to claim 1 , wherein the layer of semiconductor material is a semiconductor film disposed on an insulating layer, the insulating layer being disposed on a semiconductor substrate.

Claim 7

The semiconductor wafer according to claim 1 , wherein the PMOS device is formed with a lower thermal budget than the NMOS device.

Claim 10

The method according to claim 7 , wherein the high-K dielectric layer has a relative permittivity of about twenty or higher.

Claim 11

The method according to claim 7 , wherein the high-K dielectric layer is composed of one or more materials selected from hafnium oxide, zirconium oxide, cerium oxide, aluminum oxide, titanium oxide, yttrium oxide, barium strontium titanate and mixtures thereof.

Claim 12

The method according to claim 7 , wherein the standard-K dielectric layer is composed of one or more materials selected from a nitride or an oxynitride.

Claim 13

The method according to claim 7 , wherein formation of the NMOS device further includes forming a buffer interface layer between the high-K dielectric layer and the layer of semiconductor material.

Claim 14

The method according to claim 11 , wherein the buffer interface layer is formed from an oxide having a thickness of about 0.5 nm to about 0.7 nm.

Claim 15

The method according to claim 7 , wherein the layer of semiconductor material is a semiconductor film disposed on an insulating layer, the insulating layer being disposed on a semiconductor substrate.

Claim 16

The method according to claim 7 , wherein the step of forming the first gate electrode for the NMOS device includes depositing a first layer of gate electrode semiconductor material, doping the first layer of gate electrode semiconductor material and patterning the first layer of gate electrode semiconductor material, and the step of forming the second gate electrode for the PMOS device includes depositing a second layer of gate electrode semiconductor material, doping the second layer of gate electrode semiconductor material and patterning the second layer of gate electrode semiconductor material.

Claim 17

The method according to claim 7 , wherein the step of forming the first source and the first drain includes a first thermal cycle and the step of forming the second source and the second drain includes a second thermal cycle.

Claim 18

A semiconductor wafer comprising: a layer of semiconductor material; an NMOS device, the NMOS device including: a first source, a first drain and a first body formed from the layer of semiconductor material, the first body disposed between the first source and the first drain; and a first gate formed over the first body and having a first gate electrode defining a first channel interposed between the first source and the first drain, the first gate electrode separated from the layer of semiconductor material by a high-K gate dielectric, wherein the high-K gate dielectric is disposed on a silicon oxide buffer interface layer and the buffer interface layer is in contact with the layer of semiconductor material; and a PMOS device, the PMOS device including: a second source, a second drain and a second body formed from the layer of semiconductor material, the second body disposed between the second source and the second drain; and a second gate formed over the second body and having a second gate electrode defining a second channel interposed between the second source and the second drain, the second gate electrode separated from the layer of semiconductor material by a standard-K gate dielectric.

Claim 19

A semiconductor wafer comprising: a layer of semiconductor material; an NMOS device, the NMOS device including: a first source, a first drain and a first body formed from the layer of semiconductor material, the first body disposed between the first source and the first drain; and a first gate formed over the first body and having a first gate electrode defining a first channel interposed between the first source and the first drain, the first gate electrode separated from the layer of semiconductor material by a high-K gate dielectric, wherein the high-K gate dielectric is disposed on a silicon oxide buffer interface layer and the buffer interface layer is in contact with the layer of semiconductor material; and a PMOS device, the PMOS device including: a second source, a second drain and a second body formed from the layer of semiconductor material, the second body disposed between the second source and the second drain; and a second gate formed over the second body and having a second gate electrode defining a second channel interposed between the second source and the second drain, the second gate electrode separated from the layer of semiconductor material by a standard-K gate dielectric.

Claim 20

The semiconductor wafer according to claim 16 , wherein the high-K gate dielectric has a relative permittivity of about twenty or higher.

Claim 21

The semiconductor wafer according to claim 16 , wherein the high-K gate dielectric is composed of one or more materials selected from hafnium oxide, zirconium oxide, cerium oxide, aluminum oxide, titanium oxide, yttrium oxide, barium strontium titanate and mixtures thereof.

Claim 22

The semiconductor wafer according to claim 16 , wherein the standard-K gate dielectric is composed of one or more materials selected from a nitride or an oxynitride.

Claim 23

The semiconductor wafer according to claim 16 , wherein the buffer interface layer has a thickness of about 0.5 nm to about 0.7 nm.

Claim 24

The semiconductor wafer according to claim 16 , wherein the layer of semiconductor material is a semiconductor film disposed on an insulating layer, the insulating layer being disposed on a semiconductor substrate.

Claim 25

The semiconductor wafer according to claim 16 , wherein the PMOS device is formed with a lower thermal budget than the NMOS device.

Claim 26

A semiconductor wafer comprising: a layer of semiconductor material; an NMOS device, the NMOS device including: a first source, a first drain and a first body formed from the layer of semiconductor material, the first body disposed between the first source and the first drain; and a first gate formed over the first body and having a first gate electrode defining a first channel interposed between the first source and the first drain, the first gate electrode separated from the layer of semiconductor material by a high-K gate dielectric; and a PMOS device, the PMOS device including: a second source, a second drain and a second body formed from the layer of semiconductor material, the second body disposed between the second source and the second drain; and a second gate formed over the second body and having a second gate electrode defining a second channel interposed between the second source and the second drain, wherein the second gate electrode is disposed on a standard-K gate dielectric layer that extends from the second gate electrode to the layer of semiconductor material and is made from a substantially uniform layer composed of a material selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride.

Claim 27

A semiconductor wafer comprising: a layer of semiconductor material; an NMOS device, the NMOS device including: a first source, a first drain and a first body formed from the layer of semiconductor material, the first body disposed between the first source and the first drain; and a first gate formed over the first body and having a first gate electrode defining a first channel interposed between the first source and the first drain, the first gate electrode separated from the layer of semiconductor material by a high-K gate dielectric; and a PMOS device, the PMOS device including: a second source, a second drain and a second body formed from the layer of semiconductor material, the second body disposed between the second source and the second drain; and a second gate formed over the second body and having a second gate electrode defining a second channel interposed between the second source and the second drain, wherein the second gate electrode is disposed on a standard-K gate dielectric layer that extends from the second gate electrode to the layer of semiconductor material and is made from a substantially uniform layer composed of a material selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride.

Claim 28

The semiconductor wafer according to claim 23 , wherein the high-K gate dielectric has a relative permittivity of about twenty or higher.

Claim 29

The semiconductor wafer according to claim 23 , wherein the high-K gate dielectric is composed of one or more materials selected from hafnium oxide, zirconium oxide, cerium oxide, aluminum oxide, titanium oxide, yttrium oxide, barium strontium titanate and mixtures thereof.

Claim 30

The semiconductor wafer according to claim 23 , the standard-K gate dielectric is made from silicon nitride.

Claim 31

The semiconductor wafer according to claim 23 , wherein the standard-K gate dielectric is made form silicon oxynitride.

Claim 32

The semiconductor wafer according to claim 23 , further comprising a buffer interface disposed between the high-K gate dielectric and the layer of semiconductor material.

Claim 33

The semiconductor wafer according to claim 28 , wherein the buffer interface is formed from an oxide having a thickness of about 0.5 nm to about 0.7 nm.

Claim 34

The semiconductor wafer according to claim 23 , wherein the layer of semiconductor material is a semiconductor film disposed on an insulating layer, the insulating layer being disposed on a semiconductor substrate.

Claim 35

The semiconductor wafer according to claim 23 , wherein the PMOS device is formed with a lower thermal budget than the NMOS device.