Patent US6526549B1 successfully refreshed from Google Patents.
US6526549B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hierarchical parasitic capacitance extraction for ultra large scale integrated circuits
Assignee: Oracle America Inc
•
Filing: 2000-09-14
•
Granted: 2003-02-25
•
Expires: 2020-09-14
Abstract
Abstract A method for extracting parasitic capacitance from an integrated circuit layout includes decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions. The method further includes summing capacitances between the conductive segments in a selected net and the other conductive segments in the integrated circuit layout that are aligned with the conductive segments in the selected net and multiplying the sum by a first scaling factor to obtain a first capacitance value. The method further includes summing capacitances between the conductive segments in the selected net and the other conductive segments in the integrated circuit layout that are transverse to the conductive segments in the selected net to obtain a second capacitance value. The first capacitance value and the second capacitance value are added together to obtain a total capacitance value for the selected net.
Inventors
- 👤 Eileen H. You
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:00
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/36; G06F30/367
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
119 words
A method for extracting parasitic capacitance from an integrated circuit layout, comprising: decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions; summing capacitances between the conductive segments in a selected net and the other conductive segments that are aligned with the conductive segments in the selected net and multiplying the sum by a scaling factor to obtain a first capacitance value; summing capacitances between the conductive segments in the selected net and the other conductive segments that are transverse to the conductive segments in the selected net to obtain a second capacitance value; and summing the first capacitance value and second capacitance value to obtain a total capacitance value for the selected net.
Claim 2
Independent Claim
119 words
A method for extracting parasitic capacitance from an integrated circuit layout, comprising: decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions; summing capacitances between the conductive segments in a selected net and the other conductive segments that are aligned with the conductive segments in the selected net and multiplying the sum by a scaling factor to obtain a first capacitance value; summing capacitances between the conductive segments in the selected net and the other conductive segments that are transverse to the conductive segments in the selected net to obtain a second capacitance value; and summing the first capacitance value and second capacitance value to obtain a total capacitance value for the selected net.
Claim 3
Dependent Claim
35 words
The method of claim 1 , wherein summing capacitances between the conductive segments in the selected net and the other conductive segments includes identifying the conductive segments within a selected distance from the selected net.
Claim 4
Dependent Claim
46 words
The method of claim 2 , wherein summing capacitances between the conductive segments in the selected net and the other conductive segments includes approximating the capacitances between the conductive segments in the selected net and the other conductive segments outside of the selected distance to zero.
Claim 5
Dependent Claim
20 words
The method of claim 1 , wherein the scaling factor is a Miller scaling factor ranging from 0 to 2.
Claim 6
Independent Claim
129 words
A method for extracting parasitic capacitance from an integrated circuit layout, comprising: decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions; summing capacitances between the conductive segments in the selected net and the other conductive segments that are aligned with the conductive segments in the selected net and multiplying the sum by a first scaling factor to obtain a first capacitance value; summing capacitances between the conductive segments in the selected net and the other conductive segments that are transverse to the conductive segments in the selected net and multiplying the sum by a second scaling factor to obtain a second capacitance value; and summing the first capacitance value and second capacitance value to obtain a total capacitance value for the selected net.
Claim 7
Independent Claim
129 words
A method for extracting parasitic capacitance from an integrated circuit layout, comprising: decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions; summing capacitances between the conductive segments in the selected net and the other conductive segments that are aligned with the conductive segments in the selected net and multiplying the sum by a first scaling factor to obtain a first capacitance value; summing capacitances between the conductive segments in the selected net and the other conductive segments that are transverse to the conductive segments in the selected net and multiplying the sum by a second scaling factor to obtain a second capacitance value; and summing the first capacitance value and second capacitance value to obtain a total capacitance value for the selected net.
Claim 8
Dependent Claim
35 words
The method of claim 5 , wherein summing capacitances between the conductive segments in the selected net and the other conductive segments includes identifying the conductive segments within a selected distance from the selected net.
Claim 9
Dependent Claim
46 words
The method of claim 6 , wherein summing capacitances between the conductive segments in the selected net and the other conductive segments includes approximating the capacitances between the conductive segments in the selected net and the other conductive segments outside of the selected distance to zero.
Claim 10
Dependent Claim
22 words
The method of claim 5 , wherein the first and second scaling factors are Miller scaling factor ranging from 0 to 2.
Claim 11
Dependent Claim
75 words
An extraction tool for an integrated circuit layout, comprising: a geometric processing engine which receives the integrated circuit layout and decomposes nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions; and a capacitance solver which computes the capacitance of a selected net in the integrated circuit based on the orientation of the conductive segments in the selected net with respect to the other conductive segments in the integrated circuit layout.
Claim 12
Dependent Claim
75 words
An extraction tool for an integrated circuit layout, comprising: a geometric processing engine which receives the integrated circuit layout and decomposes nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions; and a capacitance solver which computes the capacitance of a selected net in the integrated circuit based on the orientation of the conductive segments in the selected net with respect to the other conductive segments in the integrated circuit layout.
Claim 13
Dependent Claim
120 words
The extraction tool of claim 9 , wherein the capacitance solver includes a computer-readable medium having stored thereon instructions which are executable by a processor, the instructions for: summing capacitances between the conductive segments in the selected net and the other conductive segments that are aligned with the conductive segments in the selected net and multiplying the sum by a scaling factor to obtain a first capacitance value; summing capacitances between the conductive segments in the selected net and the other conductive segments that are transverse to the conductive segments in the selected net to obtain a second capacitance value; and summing the first capacitance value and second capacitance value to obtain a total capacitance value for the selected net.
Claim 14
Dependent Claim
130 words
The extraction tool of claim 9 , wherein the capacitance solver includes a computer-readable medium having stored thereon instructions which are executable by a processor, the instructions for: summing capacitances between the conductive segments in the selected net and the other conductive segments that are aligned with the conductive segments in the selected net and multiplying the sum by a first scaling factor to obtain a first capacitance value; summing capacitances between the conductive segments in the selected net and the other conductive segments that are transverse to the conductive segments in the selected net and multiplying the sum by a second scaling factor to obtain a second capacitance value; and summing the first capacitance value and second capacitance value to obtain a total capacitance value for the selected net.
References Cited (Backward Citations)
US5629860A
Cited
US5901063A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-02-24 | 2006-08-26 | 2007-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-02-24 | 2010-08-26 | 2011-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-02-24 | 2014-08-26 | 2015-02-25 | $7700.00 | Window Closed / Lapsed |