US6525988B2
Expired / Lapsed
US
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Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same
Assignee: Samsung Electronics Co Ltd
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Filing: 2001-06-19
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Granted: 2003-02-25
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Expires: 2021-06-19
Abstract
Abstract Clock generating circuits for a semiconductor memory device are provided. The clock generating circuits include a delay locked loop (DLL) circuit that generates an internal clock signal for the semiconductor memory device. A control circuit activates the delay locked loop circuit for a predetermined time when the semiconductor memory device transitions from a self refresh mode, in which the DLL circuit is deactivated, to a standby mode. The control circuit may also be configured to deactivate the DLL circuit when the semiconductor memory device transitions from a power down mode, in which the DLL circuit is activated, to the standby mode. The semiconductor memory device may be a dynamic random access memory device and the predetermined time may be a number of clock cycles of the internal clock signal. Methods for operating the same are also provided.
Inventors
- 👤 Dong-ryul Ryu
- 👤 Chi-wook Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C8/00; G11C8/18; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; G11C2207/00; G11C2207/22; G11C2207/2227; H03L7/0802
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
67 words
A clock generating circuit for a semiconductor memory device, the clock generating circuit comprising: a delay locked loop (DLL) circuit that generates an internal clock signal for the semiconductor memory device; and a control circuit that activates the delay locked loop circuit for a predetermined time when the semiconductor memory device transitions from a self-refresh mode in which the DLL circuit is deactivated to a standby mode.
Claim 2
Dependent Claim
67 words
A clock generating circuit for a semiconductor memory device, the clock generating circuit comprising: a delay locked loop (DLL) circuit that generates an internal clock signal for the semiconductor memory device; and a control circuit that activates the delay locked loop circuit for a predetermined time when the semiconductor memory device transitions from a self-refresh mode in which the DLL circuit is deactivated to a standby mode.
Claim 3
Dependent Claim
39 words
The circuit of claim 1 wherein the control circuit is further configured to deactivate the DLL circuit when the semiconductor memory device transitions from a power down mode in which the DLL circuit is activated to the standby mode.
Claim 4
Dependent Claim
30 words
The circuit of claim 2 wherein the semiconductor memory device comprises a dynamic random access memory (DRAM) device and wherein the power down mode comprises a precharge power down mode.
Claim 5
Dependent Claim
96 words
The circuit of claim 2 wherein the control circuit comprises: a first control circuit that generates a control signal that is enabled for the predetermined time responsive to a first signal that indicates the semiconductor memory device has transitioned from the self refresh mode to the standby mode; and a second control circuit that activates the DLL circuit responsive to the first signal and deactivates the DLL circuit responsive to the control signal and responsive to a second signal that indicates the semiconductor memory device has transitioned from the power down mode to the standby mode.
Claim 6
Dependent Claim
46 words
The circuit of claim 4 wherein the first control circuit comprises: a control signal generating circuit that outputs the control signal responsive to the first signal and a time out signal; and a counter circuit that generates the time out signal responsive to the control signal.
Claim 7
Dependent Claim
76 words
The circuit of claim 5 wherein the second control circuit comprises: a set pulse generating circuit that generates a set pulse signal responsive to the first signal; a reset pulse generating circuit that generates a reset pulse signal responsive to the control signal; and a standby signal generating circuit that activates the DLL circuit responsive to the set pulse and deactivates the DLL circuit responsive to the reset pulse signal and responsive to the second signal.
Claim 8
Dependent Claim
48 words
The circuit of claim 6 wherein the set pulse generating circuit further comprises a delay circuit that determines a pulse width of the set pulse signal and wherein the reset pulse generating circuit further comprises a delay circuit that determines a pulse width of the reset pulse signal.
Claim 9
Dependent Claim
18 words
The circuit of claim 7 wherein the semiconductor memory device comprises a dynamic random access memory (DRAM) device.
Claim 10
Dependent Claim
21 words
The circuit of claim 8 wherein the predetermined time is no less than an expected lock time for the DLL circuit.
Claim 11
Dependent Claim
20 words
The circuit of claim 7 wherein the predetermined time comprises a number of clock cycles of the internal clock signal.
Claim 12
Dependent Claim
30 words
The circuit of claim 8 wherein the semiconductor memory device comprises a dynamic random access memory (DRAM) device and wherein the power down mode comprises a precharge power down mode.
Claim 13
Dependent Claim
73 words
The circuit of claim 1 wherein the control circuit comprises: a first control circuit that generates a control signal that is enabled for the predetermined time responsive to a first signal that indicates the semiconductor memory device has transitioned from the self refresh mode to the standby mode; and a second control circuit that activates the DLL circuit responsive to the first signal and deactivates the DLL circuit responsive to the control signal.
Claim 14
Dependent Claim
46 words
The circuit of claim 12 wherein the first control circuit comprises: a control signal generating circuit that outputs the control signal responsive to the first signal and a time out signal; and a counter circuit that generates the time out signal responsive to the control signal.
Claim 15
Dependent Claim
70 words
The circuit of claim 13 wherein the second control circuit comprises: a set pulse generating circuit that generates a set pulse signal responsive to the first signal; a reset pulse generating circuit that generates a reset pulse signal responsive to the control signal; and a standby signal generating circuit that activates the DLL circuit responsive to the set pulse and deactivates the DLL circuit responsive to the reset pulse signal.
Claim 16
Dependent Claim
18 words
The circuit of claim 14 wherein the semiconductor memory device comprises a dynamic random access memory (DRAM) device.
Claim 17
Dependent Claim
21 words
The circuit of claim 14 wherein the predetermined time is no less than an expected lock time for the DLL circuit.
Claim 18
Dependent Claim
20 words
The circuit of claim 14 wherein the predetermined time comprises a number of clock cycles of the internal clock signal.
Claim 19
Dependent Claim
18 words
The circuit of claim 1 wherein the semiconductor memory device comprises a dynamic random access memory (DRAM) device.
Claim 20
Dependent Claim
21 words
The circuit of claim 1 wherein the predetermined time is no less than an expected lock time for the DLL circuit.
Claim 21
Dependent Claim
20 words
The circuit of claim 1 wherein the predetermined time comprises a number of clock cycles of the internal clock signal.
Claim 22
Independent Claim
77 words
A method for controlling a clock generating circuit of a semiconductor memory device, the method comprising the steps of: activating a delay locked loop (DLL) circuit of the clock generating circuit when the semiconductor memory device transitions to a standby mode from a self refresh mode in which the DLL circuit is deactivated; and then deactivating the DLL circuit a predetermined time after the semiconductor memory device transitions to the standby mode from the self refresh mode.
Claim 23
Independent Claim
77 words
A method for controlling a clock generating circuit of a semiconductor memory device, the method comprising the steps of: activating a delay locked loop (DLL) circuit of the clock generating circuit when the semiconductor memory device transitions to a standby mode from a self refresh mode in which the DLL circuit is deactivated; and then deactivating the DLL circuit a predetermined time after the semiconductor memory device transitions to the standby mode from the self refresh mode.
Claim 24
Dependent Claim
36 words
The method of claim 21 further comprising the step of deactivating the DLL circuit when the semiconductor memory device transitions to the standby mode from a power down mode in which the DLL circuit is activated.
Claim 25
Dependent Claim
30 words
The method of claim 22 wherein the semiconductor memory device comprises a dynamic random access memory (DRAM) device and wherein the power down mode comprises a precharge power down mode.
Claim 26
Dependent Claim
21 words
The method of claim 22 wherein the predetermined time is no less than an expected lock time for the DLL circuit.
Claim 27
Dependent Claim
25 words
The method of claim 22 wherein the predetermined time comprises a number of clock cycles of an internal clock signal generated by the DLL circuit.
Claim 28
Dependent Claim
122 words
A semiconductor memory device, which has a self refresh mode, a precharge power down mode, and a standby mode and operates in synchronization with a system clock signal; comprising: a delay locked loop circuit for generating an internal clock signal in synchronization with the system clock signal; and a control circuit for activating the delay locked loop circuit during a predetermined clock cycle of the internal clock signal when the mode of the semiconductor memory device is converted from the self refresh mode into the standby mode and then, deactivating the delay locked loop circuit and deactivating the delay locked loop circuit when the mode of the semiconductor memory device is converted from the precharge power down mode into the standby mode.
Claim 29
Dependent Claim
122 words
A semiconductor memory device, which has a self refresh mode, a precharge power down mode, and a standby mode and operates in synchronization with a system clock signal; comprising: a delay locked loop circuit for generating an internal clock signal in synchronization with the system clock signal; and a control circuit for activating the delay locked loop circuit during a predetermined clock cycle of the internal clock signal when the mode of the semiconductor memory device is converted from the self refresh mode into the standby mode and then, deactivating the delay locked loop circuit and deactivating the delay locked loop circuit when the mode of the semiconductor memory device is converted from the precharge power down mode into the standby mode.
Claim 30
Dependent Claim
119 words
The semiconductor memory device of claim 26 , wherein the control circuit comprises: a first control circuit for generating a control signal, which is enabled in response to a first signal for informing that the mode of the semiconductor memory device is converted from the self refresh mode into the standby mode and is disabled after the predetermined clock cycle has passed; and a second control circuit for activating the delay locked loop circuit in response to the first signal and deactivating the delay locked loop circuit in response to the control signal or a second signal for informing that the mode of the semiconductor memory device is converted from the precharge power down mode into the standby mode.
Claim 31
Dependent Claim
64 words
The semiconductor memory device of claim 27 , wherein the first control circuit comprises: a control signal generating circuit for generating the control signal in response to the first signal and a third signal for informing that the predetermined clock cycle has passed; and a counter circuit for generating the third signal by counting the internal clock signal in response to the control signal.
Claim 32
Dependent Claim
117 words
The semiconductor memory device of claim 27 , wherein the second control circuit comprises: a first pulse signal generating circuit for generating a first pulse signal in response to the first signal; a second pulse signal generating circuit for generating a second pulse signal in response to the disablement of the control signal; and a standby signal generating circuit for generating a standby signal for activating the delay locked loop circuit in response to the first pulse signal and deactivating the delay locked loop circuit in response to the second pulse signal or a signal for informing that the mode of the semiconductor memory device is converted from the precharge power down mode into the standby mode.
Claim 33
Dependent Claim
28 words
The semiconductor memory device of claim 26 , wherein the predetermined clock cycle is larger than a time taken for the delay locked loop circuit to be locked.
Claim 34
Independent Claim
123 words
A method for controlling the power down of a semiconductor memory device, which comprises a delay locked loop circuit for generating an internal clock signal in synchronization with a system clock signal and has a self refresh mode, a precharge power down mode, and a standby mode, comprising the steps of: (a) activating the delay locked loop circuit during a predetermined clock cycle of the internal clock signal when the mode of the semiconductor memory device is converted from the self refresh mode into the standby mode and then, deactivating the delay locked loop circuit; and (b) deactivating the delay locked loop circuit when the mode of the semiconductor memory device is converted from the precharge power down mode into the standby mode.
Claim 35
Independent Claim
123 words
A method for controlling the power down of a semiconductor memory device, which comprises a delay locked loop circuit for generating an internal clock signal in synchronization with a system clock signal and has a self refresh mode, a precharge power down mode, and a standby mode, comprising the steps of: (a) activating the delay locked loop circuit during a predetermined clock cycle of the internal clock signal when the mode of the semiconductor memory device is converted from the self refresh mode into the standby mode and then, deactivating the delay locked loop circuit; and (b) deactivating the delay locked loop circuit when the mode of the semiconductor memory device is converted from the precharge power down mode into the standby mode.
Claim 36
Dependent Claim
86 words
The method of claim 31 , wherein the step (a) comprises the steps of: (a1) generating a control signal, which is enabled in response to a first signal for informing that the mode of the semiconductor memory device is converted from the self refresh mode into the standby mode and is disabled after the redetermined clock cycle has passed; and (a2) activating the delay locked loop circuit in response to the first signal and deactivating the delay locked loop circuit when the control signal is disabled.
Claim 37
Dependent Claim
56 words
The method of claim 32 , wherein the step (a1) comprises the steps of: (a11) generating the control signal in response to the first signal and a second signal for informing that the predetermined clock cycle has passed; and (a12) generating the second signal by counting the internal clock signal in response to the control signal.
Claim 38
Dependent Claim
75 words
The method of claim 32 , wherein the step (a2) comprises the steps of: (a21) generating a first pulse signal in response to the first signal; (a22) generating a second pulse signal in response to the disablement of the control signal; and (a23) generating a standby signal for activating the delay locked loop circuit in response to the first pulse signal and deactivating the delay locked loop circuit in response to the second pulse signal.
Claim 39
Dependent Claim
52 words
The method of claim 31 , wherein the step (b) comprises the step of generating a standby signal for deactivating the delay locked loop circuit in response to a signal for informing that the mode of the semiconductor memory device is converted from the precharge power down mode into the standby mode.
Claim 40
Dependent Claim
26 words
The method of claim 31 , wherein the predetermined clock cycle is larger than a time taken for the delay locked loop circuit to be locked.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-02-24 | 2006-08-26 | 2007-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-02-24 | 2010-08-26 | 2011-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-02-24 | 2014-08-26 | 2015-02-25 | $7700.00 | Window Closed / Lapsed |