US6522562B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Content addressable memory cell having improved layout
Assignee: Mosaid Technologies Inc
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Filing: 2001-06-29
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Granted: 2003-02-18
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Expires: 2021-06-29
Abstract
Abstract A CAM cell comprises a pair of SRAM cells, each of which comprise a pair of cross coupled inverters for storing a data value and a pair of access devices for accessing a complementary pair of bit lines. The CAM cell further comprises a pair of compare circuits, each for comparing said data value stored in one of said SRAM cells with a search data value provided on a corresponding search line. The CAM cell has an equivalent number of n-channel and p-channel devices. The CAM cell uses p-channel transistors as access transistors to the SRAM cells in order to improve the efficiency of the layout of the cell array. The implementation ensures a balanced number of p-channel and n-channel devices per cell while still providing excellent functional characteristics.
Inventors
- 👤 Richard Foss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:46
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
105 words
A ternary content addressable memory (CAM) half-cell comprising: (a) a static random access memory (SRAM) cell having i. a pair of cross coupled inverters for storing a data value; and ii. a pair of access devices, each coupled between respective ones of said pair of cross coupled inverters and a pair of complementary bit lines for accessing said pair of complementary bit lines; (b) a compare circuit for comparing said data value stored in said SRAM cell with a search data value provided on a search line, said CAM cell having an equivalent number of n-channel and p-channel devices, thereby affording an improved cell layout.
Claim 2
Dependent Claim
105 words
A ternary content addressable memory (CAM) half-cell comprising: (a) a static random access memory (SRAM) cell having i. a pair of cross coupled inverters for storing a data value; and ii. a pair of access devices, each coupled between respective ones of said pair of cross coupled inverters and a pair of complementary bit lines for accessing said pair of complementary bit lines; (b) a compare circuit for comparing said data value stored in said SRAM cell with a search data value provided on a search line, said CAM cell having an equivalent number of n-channel and p-channel devices, thereby affording an improved cell layout.
Claim 3
Dependent Claim
26 words
A CAM half-cell as defined in claim 1 , wherein said cross coupled inverter comprises a pair of n-channel devices and a pair of p-channel devices.
Claim 4
Dependent Claim
25 words
A CAM half-cell as defined in claim 2 , wherein said pair of access devices comprises p-channel devices and said compare circuit comprises n-channel devices.
Claim 5
Dependent Claim
25 words
A CAM half-cell as defined in claim 2 , wherein said pair of access devices comprises n-channel devices and said compare circuit comprises p-channel devices.
Claim 6
Dependent Claim
118 words
A ternary content addressable memory (CAM) cell comprising: (a) a pair of static random access memory (SRAM) cells, each of said SRAM cells having i. a pair of cross coupled inverters for storing a data value; and ii. a pair of access devices, each coupled between respective ones of said pair of cross coupled inverters and a pair of complementary bit lines for accessing said pair of complementary bit lines; (b) a pair of compare circuits, each for comparing said data value stored in one of said SRAM cells with a search data value provided on an associated search line, said CAM cell having an equivalent number of n-channel and p-channel devices, thereby affording an improved cell layout.
Claim 7
Dependent Claim
118 words
A ternary content addressable memory (CAM) cell comprising: (a) a pair of static random access memory (SRAM) cells, each of said SRAM cells having i. a pair of cross coupled inverters for storing a data value; and ii. a pair of access devices, each coupled between respective ones of said pair of cross coupled inverters and a pair of complementary bit lines for accessing said pair of complementary bit lines; (b) a pair of compare circuits, each for comparing said data value stored in one of said SRAM cells with a search data value provided on an associated search line, said CAM cell having an equivalent number of n-channel and p-channel devices, thereby affording an improved cell layout.
Claim 8
Dependent Claim
29 words
A CAM cell as defined in claim 5 , wherein all p-channel devices are formed in one n-well region and all n-channel devices are formed in one p-well region.
Claim 9
Dependent Claim
26 words
A CAM cell as defined in claim 5 , wherein said cross coupled inverter comprises a pair of n-channel devices and a pair of p-channel devices.
Claim 10
Dependent Claim
25 words
A CAM cell as defined in claim 7 , wherein said pair of access devices comprises p-channel devices and said compare circuit comprises n-channel devices.
Claim 11
Dependent Claim
25 words
A CAM cell as defined in claim 7 , wherein said pair of access devices comprises n-channel devices and said compare circuit comprises p-channel devices.
Claim 12
Dependent Claim
29 words
A CAM cell as defined in claim 1 , wherein all p-channel devices are formed in one n-well region and all n-channel devices are formed in one p-well region.
Claim 13
Dependent Claim
105 words
A ternary content addressable memory (CAM) half-cell comprising: (a) a static random access memory (SRAM cells having i. a pair of cross coupled inverters for storing a data value; and ii. a pair of access devices, each coupled between respective ones of said pair of cross coupled inverters and a pair of complementary bit lines for accessing said pair of complementary bit lines; (b) a compare circuit for comparing said data value stored in said SRAM cell with a search data value provided on a search line, said CAM cell having only one p+ region to n+ region separation, thereby affording an improved cell layout.
Claim 14
Dependent Claim
105 words
A ternary content addressable memory (CAM) half-cell comprising: (a) a static random access memory (SRAM cells having i. a pair of cross coupled inverters for storing a data value; and ii. a pair of access devices, each coupled between respective ones of said pair of cross coupled inverters and a pair of complementary bit lines for accessing said pair of complementary bit lines; (b) a compare circuit for comparing said data value stored in said SRAM cell with a search data value provided on a search line, said CAM cell having only one p+ region to n+ region separation, thereby affording an improved cell layout.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-02-17 | 2006-08-19 | 2007-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-02-17 | 2010-08-19 | 2011-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-02-17 | 2014-08-19 | 2015-02-18 | $7700.00 | Window Closed / Lapsed |