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US6240004B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Low-voltage content addressable memory cell with a fast tag-compare capability using partially-depleted SOI CMOS dynamic-threshold techniques

Assignee: Transpacific IP Ltd
•
Filing: 2000-06-19
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Granted: 2001-05-29
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Expires: 2020-06-19
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Abstract

Abstract This invention discloses a content addressable memory (CAM) cell having a SRAM portion and a tag-compare portion. The tag-compare portion includes six NMOS transistors, designated as M 7 to M 12, wherein a source of M 7 is connected to a drain of M 8, a drain of M 7 is connected to a match line ML, a source of M 8 is grounded; a body of M 7 and a body of M 8 are tied together at a source of M 11, a gate of M 7 and a gate of M 11 are tied together to a first node n 1 , a gate of M 8 and a drain of M 11 are connected to a first digit line DLB; and a source of M 9 is connected to a drain of M 10, a drain of M 9 is connected to said match line ML, a source of M 10 is grounded; a body of M 9 and a body of M 10 are tied together at a source of M 12, a gate of M 9 and a gate of M 12 are tied together to a second node n 2, a gate of M 10 and a drain of M 12 are connected to a second digit line DL. The first and second nodes n 1 and n 2 are internal storage nodes of the SRAM portion.

Inventors

  • 👤 James B. Kuo
  • 👤 Sheng-Che Liu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 02:56
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 207 words
A content addressable memory cell comprising a tag-compare portion comprising six NMOS transistors, designated as M 7 to M 12 , wherein a source of M 7 is connected to a drain of M 8 , a drain of M 7 is connected to a match line, a source of M 8 is grounded; a body of M 7 and a body of M 8 are tied together at a source of M 11 , a gate of M 7 and a gate of M 11 are tied together to a first node n 1 , a gate of M 8 and a drain of M 11 are connected to a first digit line; and a source of M 9 is connected to a drain of M 10 , a drain of M 9 is connected to said match line, a source of M 10 is grounded; a body of M 9 and a body of M 10 are tied together at a source of M 12 , a gate of M 9 and a gate of M 12 are tied together to a second node n 2 , a gate of M 10 and a drain of M 12 are connected to a second digit line.
Claim 2
Dependent Claim 207 words
A content addressable memory cell comprising a tag-compare portion comprising six NMOS transistors, designated as M 7 to M 12 , wherein a source of M 7 is connected to a drain of M 8 , a drain of M 7 is connected to a match line, a source of M 8 is grounded; a body of M 7 and a body of M 8 are tied together at a source of M 11 , a gate of M 7 and a gate of M 11 are tied together to a first node n 1 , a gate of M 8 and a drain of M 11 are connected to a first digit line; and a source of M 9 is connected to a drain of M 10 , a drain of M 9 is connected to said match line, a source of M 10 is grounded; a body of M 9 and a body of M 10 are tied together at a source of M 12 , a gate of M 9 and a gate of M 12 are tied together to a second node n 2 , a gate of M 10 and a drain of M 12 are connected to a second digit line.
Claim 3
Dependent Claim 249 words
The content addressable memory cell according to claim 1 further comprising a SRAM portion containing said first node n 1 and said second node n 2 , wherein said SRAM portion comprises two PMOS's, designated as M 1 and M 2 ; and four NMOS's, designated as M 3 , M 4 , M 5 and M 6 , wherein a drain of the NMOS M 3 is connected to that of the PMOS M 1 at said first node n 1 while their gates are tied together at said second node n 2 ; a source of the PMOS M 1 is connected to a supply voltage V dd ; a drain of the NMOS M 4 is connected to that of the PMOS M 2 at the second node n 2 while their gates are tied together at the first node n 1 ; a source of the NMOS M 4 is grounded and that of the PMOS M 2 is connected to the supply voltage V dd ; the NMOS M 5 and NMOS M 6 are pass transistors, one of them M 5 is controlled by a word line via its gate, and its drain and source are connected to a first bit line and the first node n 1 respectively; another one of them M 6 is controlled by the word line via its gate, and its drain and source are connected to a second bit line and the second node n 2 respectively.

References Cited (Backward Citations)

US5999435A Cited
US6175514B1 Cited
US6157558A Cited
US6078513A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-05-28 2004-11-27 2005-05-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-05-28 2008-11-27 2009-05-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-05-28 2012-11-27 2013-05-29 $7700.00 Window Closed / Lapsed

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