Abstract This invention discloses a content addressable memory (CAM) cell having a SRAM portion and a tag-compare portion. The tag-compare portion includes six NMOS transistors, designated as M 7 to M 12, wherein a source of M 7 is connected to a drain of M 8, a drain of M 7 is connected to a match line ML, a source of M 8 is grounded; a body of M 7 and a body of M 8 are tied together at a source of M 11, a gate of M 7 and a gate of M 11 are tied together to a first node n 1 , a gate of M 8 and a drain of M 11 are connected to a first digit line DLB; and a source of M 9 is connected to a drain of M 10, a drain of M 9 is connected to said match line ML, a source of M 10 is grounded; a body of M 9 and a body of M 10 are tied together at a source of M 12, a gate of M 9 and a gate of M 12 are tied together to a second node n 2, a gate of M 10 and a drain of M 12 are connected to a second digit line DL. The first and second nodes n 1 and n 2 are internal storage nodes of the SRAM portion.
Inventors
👤 James B. Kuo
👤 Sheng-Che Liu
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-04 16:06
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
207 words
A content addressable memory cell comprising a tag-compare portion comprising six NMOS transistors, designated as M 7 to M 12 , wherein a source of M 7 is connected to a drain of M 8 , a drain of M 7 is connected to a match line, a source of M 8 is grounded; a body of M 7 and a body of M 8 are tied together at a source of M 11 , a gate of M 7 and a gate of M 11 are tied together to a first node n 1 , a gate of M 8 and a drain of M 11 are connected to a first digit line; and a source of M 9 is connected to a drain of M 10 , a drain of M 9 is connected to said match line, a source of M 10 is grounded; a body of M 9 and a body of M 10 are tied together at a source of M 12 , a gate of M 9 and a gate of M 12 are tied together to a second node n 2 , a gate of M 10 and a drain of M 12 are connected to a second digit line.
Claim 2
Dependent Claim
207 words
A content addressable memory cell comprising a tag-compare portion comprising six NMOS transistors, designated as M 7 to M 12 , wherein a source of M 7 is connected to a drain of M 8 , a drain of M 7 is connected to a match line, a source of M 8 is grounded; a body of M 7 and a body of M 8 are tied together at a source of M 11 , a gate of M 7 and a gate of M 11 are tied together to a first node n 1 , a gate of M 8 and a drain of M 11 are connected to a first digit line; and a source of M 9 is connected to a drain of M 10 , a drain of M 9 is connected to said match line, a source of M 10 is grounded; a body of M 9 and a body of M 10 are tied together at a source of M 12 , a gate of M 9 and a gate of M 12 are tied together to a second node n 2 , a gate of M 10 and a drain of M 12 are connected to a second digit line.
Claim 3
Dependent Claim
249 words
The content addressable memory cell according to claim 1 further comprising a SRAM portion containing said first node n 1 and said second node n 2 , wherein said SRAM portion comprises two PMOS's, designated as M 1 and M 2 ; and four NMOS's, designated as M 3 , M 4 , M 5 and M 6 , wherein a drain of the NMOS M 3 is connected to that of the PMOS M 1 at said first node n 1 while their gates are tied together at said second node n 2 ; a source of the PMOS M 1 is connected to a supply voltage V dd ; a drain of the NMOS M 4 is connected to that of the PMOS M 2 at the second node n 2 while their gates are tied together at the first node n 1 ; a source of the NMOS M 4 is grounded and that of the PMOS M 2 is connected to the supply voltage V dd ; the NMOS M 5 and NMOS M 6 are pass transistors, one of them M 5 is controlled by a word line via its gate, and its drain and source are connected to a first bit line and the first node n 1 respectively; another one of them M 6 is controlled by the word line via its gate, and its drain and source are connected to a second bit line and the second node n 2 respectively.