Patent US6515511B2 successfully refreshed from Google Patents.
US6515511B2
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US
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Semiconductor integrated circuit and semiconductor integrated circuit device
Assignee: NEC Corp
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Filing: 2001-02-16
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Granted: 2003-02-04
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Expires: 2021-02-16
Abstract
Abstract A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.
Inventors
- 👤 Tadahiko Sugibayashi
- 👤 Tohru Mogami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:51
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D84/90; H10D84/903; H10D84/907; H10D88/00; H10D88/01; H10D86/40; H10D86/60
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
141 words
A semiconductor integrated circuit having a plurality of basic cells which are placed in a matrix form and are connected to each other via a signal bus, wherein: each of the basic cells includes a wire selection portion and a logic gate portion, the wire selection portion having at least one thin film transistor placed in an interlayer insulating film over a semiconductor substrate, the logic gate portion has a programmable logic gate and a memory for programming the programmable logic gate, the wire selection portion has a wire switch and an input-output switch, the wire switch is connected to the signal bus and the memory, and the input-output switch is connected to the signal bus, the memory and the programmable logic gate, each of the wire switch and input-output switch being controlled by a data signal stored in the memory.
Claim 2
Dependent Claim
141 words
A semiconductor integrated circuit having a plurality of basic cells which are placed in a matrix form and are connected to each other via a signal bus, wherein: each of the basic cells includes a wire selection portion and a logic gate portion, the wire selection portion having at least one thin film transistor placed in an interlayer insulating film over a semiconductor substrate, the logic gate portion has a programmable logic gate and a memory for programming the programmable logic gate, the wire selection portion has a wire switch and an input-output switch, the wire switch is connected to the signal bus and the memory, and the input-output switch is connected to the signal bus, the memory and the programmable logic gate, each of the wire switch and input-output switch being controlled by a data signal stored in the memory.
Claim 3
Dependent Claim
36 words
A circuit as claimed in claim 1 , wherein: the data signal is written into the memory by the use of one of a ROM, an EPROM, and an EEPROM when a power supply is introduced.
Claim 4
Dependent Claim
23 words
A circuit as claimed in claim 1 , wherein: the memory comprises an SRAM, a DRAM, a ROM, an EPROM, and an EEPROM.
Claim 5
Dependent Claim
70 words
A circuit as claimed in claim 1 , wherein: the signal bus comprises a Y-direction signal bus having first wiring lines and a X-direction signal bus having second wiring lines, the wire switch has first transfer gates which are placed between the first wiring lines and the second wiring lines, a wire connection between the Y-direction signal bus and the X-direction signal bus is changed by the first transfer gate.
Claim 6
Dependent Claim
39 words
A circuit as claimed in claim 4 , wherein: the first transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor so as to structure the wire selection portion in a three-dimensional form.
Claim 7
Dependent Claim
39 words
A circuit as claimed in claim 4 , wherein: the first thin film transistor has a first gate, the first gate is connected to the memory, the memory is driven by a voltage higher than a power supply voltage.
Claim 8
Dependent Claim
60 words
A circuit as claimed in claim 4 , wherein: the programmable logic gate has an input terminal and an output terminal, the input-output switch has second transfer gates which are placed between the second wiring lines, and a wire connection between the X-direction signal bus and the input terminal and the output terminal is changed by the second transfer gate.
Claim 9
Dependent Claim
39 words
A circuit as claimed in claim 6 , wherein: the second transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor so as to structure the wire selection portion in a three-dimensional form.
Claim 10
Dependent Claim
39 words
A circuit as claimed in claim 6 , wherein: the second thin film transistor has a second gate, the second gate is connected to the memory, the memory is driven by a voltage higher than a power supply voltage.
Claim 11
Dependent Claim
65 words
A circuit as claimed in claim 1 , wherein: the programmable logic gate comprises; a switch portion which has a pair of third transfer gates, a level converter which is connected to one of the third transfer gates; an inverter which is connected to another one of the third transfer gates, and an output buffer which is given with an output of the switch portion.
Claim 12
Dependent Claim
39 words
A circuit as claimed in claim 10 , wherein: the third transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor so as to structure the logic gate portion in a three-dimensional form.
Claim 13
Dependent Claim
17 words
A circuit as claimed in claim 1 , wherein: a repeater is inserted between the basic cells.
Claim 14
Dependent Claim
16 words
A circuit as claimed in claim 1 , wherein: the basic cell comprises a neuron cell.
Claim 15
Dependent Claim
129 words
A semiconductor integrated circuit having a plurality of basic cells which are placed in a matrix form and are connected to each other via a signal bus, wherein: each of the basic cells includes a wire selection portion and a logic gate portion having transfer gates, the logic gate portion has a fixed logic gate and a memory, the wire selection portion has a wire switch and an input switch, the wire switch is connected to the signal bus, the input switch, and the memory, the input switch is connected to the signal bus and the fixed logic gate, and the fixed logic gate is connected to the signal bus, each of the wire switch and the input switch being controlled by a data signal stored in the memory.
Claim 16
Dependent Claim
129 words
A semiconductor integrated circuit having a plurality of basic cells which are placed in a matrix form and are connected to each other via a signal bus, wherein: each of the basic cells includes a wire selection portion and a logic gate portion having transfer gates, the logic gate portion has a fixed logic gate and a memory, the wire selection portion has a wire switch and an input switch, the wire switch is connected to the signal bus, the input switch, and the memory, the input switch is connected to the signal bus and the fixed logic gate, and the fixed logic gate is connected to the signal bus, each of the wire switch and the input switch being controlled by a data signal stored in the memory.
Claim 17
Dependent Claim
23 words
A circuit as claimed in claim 14 , wherein: the memory comprises an SRAM, a DRAM, a ROM, an EPROM, and an EEPROM.
Claim 18
Dependent Claim
26 words
A circuit as claimed in claim 14 , wherein: the transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor.
Claim 19
Dependent Claim
129 words
A semiconductor integrated circuit having a plurality of basic cells which are placed in a matrix form and are connected to each other via a signal bus, wherein: each of the basic cells includes a wire selection portion and a logic gate portion having transfer gates, the logic gate portion has a programmable logic gate and a memory, the wire selection portion has a wire switch and an input switch, the wire switch is connected to the signal bus, the input switch, and the memory, the input switch is connected to the signal bus and the programmable logic gate, and the programmable logic gate is connected to the signal bus, each of the wire switch and the input switch being controlled by a data signal stored in the memory.
Claim 20
Dependent Claim
129 words
A semiconductor integrated circuit having a plurality of basic cells which are placed in a matrix form and are connected to each other via a signal bus, wherein: each of the basic cells includes a wire selection portion and a logic gate portion having transfer gates, the logic gate portion has a programmable logic gate and a memory, the wire selection portion has a wire switch and an input switch, the wire switch is connected to the signal bus, the input switch, and the memory, the input switch is connected to the signal bus and the programmable logic gate, and the programmable logic gate is connected to the signal bus, each of the wire switch and the input switch being controlled by a data signal stored in the memory.
Claim 21
Dependent Claim
23 words
A circuit as claimed in claim 17 , wherein: the memory comprises an SRAM, a DRAM, a ROM, an EPROM, and an EEPROM.
Claim 22
Dependent Claim
26 words
A circuit as claimed in claim 17 , wherein: the transfer gate comprises an n-channel enhancement type thin-film transistor or an n-channel depletion type thin-film transistor.
Claim 23
Dependent Claim
78 words
A semiconductor integrated circuit device having a plurality of basic cells which are placed in a matrix form and are formed on a semiconductor substrate, wherein: each of the basic cells includes a wire selection portion and a logic gate portion, the logic gate portion has a MOS transistor, the wire selection portion has a thin-film transistor serving as a transfer gate, the wire selection portion being placed over the logic gate portion via an interlayer insulating film.
Claim 24
Dependent Claim
78 words
A semiconductor integrated circuit device having a plurality of basic cells which are placed in a matrix form and are formed on a semiconductor substrate, wherein: each of the basic cells includes a wire selection portion and a logic gate portion, the logic gate portion has a MOS transistor, the wire selection portion has a thin-film transistor serving as a transfer gate, the wire selection portion being placed over the logic gate portion via an interlayer insulating film.
Claim 25
Dependent Claim
24 words
A device as claimed in claim 20 , wherein: the thin-film transistor comprises an n-channel enhancement type or an n-channel depletion type thin-film transistor.
Claim 26
Dependent Claim
33 words
A device as claimed in claim 20 , wherein: at least a pair of wiring patterns are formed in the interlayer insulating film, and the thin-film transistor is placed between the wiring patterns.
Claim 27
Dependent Claim
23 words
A device as claimed in claim 20 , wherein: the thin-film transistor comprises any one of a lateral type and a vertical type.
Claim 28
Dependent Claim
29 words
A device as claimed in claim 20 , wherein: the thin-film transistor has at least a channel region, and the channel region is formed by a non-doped polysilicon film.
References Cited (Backward Citations)
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JPH06104405A
Cited
JPH0732200A
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JPH09148440A
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JPH1117107A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-02-03 | 2006-08-05 | 2007-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-02-03 | 2010-08-05 | 2011-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-02-03 | 2014-08-05 | 2015-02-04 | $7700.00 | Window Closed / Lapsed |