Patent US6515335B1 successfully refreshed from Google Patents.
US6515335B1
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Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
Assignee: GlobalFoundries US Inc
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Filing: 2002-01-04
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Granted: 2003-02-04
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Expires: 2022-01-04
Abstract
Abstract A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.
Inventors
- 👤 Silke H. Christiansen
- 👤 Alfred Grill
- 👤 Patricia M. Mooney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:37
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10P14/00; H10P14/20; H10P14/22; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/32; H10P14/3202; H10P14/3204; H10P14/3211; H10P14/3242; H10P14/3244; H10P14/3248; H10P14/3251; H10P14/3254; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P90/1908; H10P95/00; H10P95/90; H10W; H10W10/00; H10W10/10; H10W10/181
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
65 words
A semiconductor structure comprising: a Si substrate having a top surface; a first insulating layer atop of said Si substrate; a first single crystalline relaxed SiGe layer atop said first insulating layer, wherein said first single crystalline relaxed SiGe layer has a uniform composition, is less than 200 nm thick, and has a threading dislocation density of less than about 10 7 cm −2 .
Claim 2
Dependent Claim
65 words
A semiconductor structure comprising: a Si substrate having a top surface; a first insulating layer atop of said Si substrate; a first single crystalline relaxed SiGe layer atop said first insulating layer, wherein said first single crystalline relaxed SiGe layer has a uniform composition, is less than 200 nm thick, and has a threading dislocation density of less than about 10 7 cm −2 .
Claim 3
Dependent Claim
32 words
The semiconductor structure of claim 1 further comprising an optional intermediate layer formed atop said first insulating layer and said single crystalline relaxed SiGe layer being formed atop said optional intermediate layer.
Claim 4
Dependent Claim
19 words
The semiconductor structure of claim 1 wherein said first insulating is a buried oxide layer of a silicon-on-insulator substrate.
Claim 5
Dependent Claim
25 words
The semiconductor structure of claim 1 wherein said first single crystalline relaxed SiGe layer has a thickness of from about 15 to about 200 nm.
Claim 6
Dependent Claim
31 words
The semiconductor structure of claim 1 wherein said threading dislocation density of said first single crystalline relaxed SiGe layer is from about 10 3 to about 10 6 cm −2 .
Claim 7
Dependent Claim
24 words
The semiconductor structure of claim 1 wherein said first single crystalline relaxed SiGe layer comprises from about 5 to about 40 atomic percent Ge.
Claim 8
Dependent Claim
24 words
The semiconductor structure of claim 1 wherein said first single crystalline relaxed SiGe layer comprises from about 15 to about 35 atomic percent Ge.
Claim 9
Dependent Claim
20 words
The semiconductor structure of claim 1 further comprising a homo-epitaxial SiGe layer formed atop said single crystalline relaxed SiGe layer.
Claim 10
Dependent Claim
25 words
The semiconductor structure of claim 1 further comprising a pseudomorphic layer of strained single crystalline Si grown on said first single crystalline relaxed SiGe layer.
Claim 11
Dependent Claim
75 words
The semiconductor structure of claim 1 further comprising a pseudomorphic strained Si layer atop said first single crystalline SiGe layer, a second single crystalline SiGe layer, of same composition as said first SiGe layer, a layer of single crystalline n+ doped, relaxed SiGe layer having the same composition as that of single crystalline relaxed SiGe layer, and a pseudomorphic layer of strained single crystalline Si formed on said single crystalline n+ doped, relaxed SiGe layer.
Claim 12
Dependent Claim
109 words
The semiconductor structure of claim 1 further comprising a layer of single crystalline p+doped, relaxed SiGe layer having the same composition as that of the single crystalline relaxed SiGe layer formed atop said single crystalline SiGe layer, a single crystalline SiGe layer of the same composition present atop said p+ doped, relaxed SiGe layer, a pseudomorphic layer of compressively strained single crystalline SiGe formed on said single crystalline, relaxed SiGe layer, a single crystalline SiGe layer and having the same composition as p+ doped, relaxed SiGe layer formed atop said pseudomorphic compressively strained SiGe layer, and a pseudomorphic Si cap layer formed atop said strained single crystalline Si layer.
Claim 13
Dependent Claim
75 words
The semiconductor structure of claim 1 further comprising a pseudomorphic strained Si layer atop said first single crystalline SiGe layer a second single crystalline SiGe layer, of same composition as said first SiGe layer, a layer of single crystalline n+ doped, relaxed SiGe layer having the same composition as that of single crystalline relaxed SiGe layer, and a pseudomorphic layer of strained single crystalline Si formed on said single crystalline n+ doped, relaxed SiGe layer.
Claim 14
Dependent Claim
59 words
The semiconductor structure of claim 1 further comprising a superlattice structure formed atop said single crystalline relaxed SiGe layer, wherein said superlattice structure comprises alternating layers of Si 1−x−y Ge x C y and Si 1−z−w Ge z C w , where x and y are different from z and w, respectively, and x and y can equal 0.
Claim 15
Dependent Claim
42 words
The semiconductor structure of claim 2 wherein said optional intermediate layer comprises a single crystalline relaxed SiGe layer of graded composition having between 0 atomic % Ge and the same atomic percent Ge present in said first single crystalline relaxed SiGe layer.
Claim 16
Dependent Claim
22 words
The semiconductor structure of claim 2 wherein said optional intermediate layer has a thickness of from about 0 to about 50 nm.
Claim 17
Dependent Claim
23 words
The semiconductor structure of claim 8 wherein said homo-epitaxial SiGe layer has the same composition as said first single crystalline relaxed SiGe layer.
Claim 18
Dependent Claim
22 words
The semiconductor structure of claim 8 further comprising a pseudomorphic layer of strained single crystalline Si grown on said homo-epitaxial SiGe layer.
Claim 19
Dependent Claim
57 words
The semiconductor structure of claim 8 further comprising a superlattice structure formed atop said homo-epitaxial SiGe layer, wherein said superlattice structure comprises alternating layers of Si 1−x−y Ge x C y and Si 1−z−w Ge z C w , where x and y are different from z and w, respectively, and x and y can equal 0.
Claim 20
Dependent Claim
22 words
The semiconductor structure of claim 16 wherein said homo-epitaxial SiGe layer has a thickness of from about 100 to about 1000 nm.
Claim 21
Dependent Claim
35 words
The semiconductor structure of claim 9 further comprising at least one semiconductor device formed in said pseudomorphic layer of strained single crystalline Si and optionally extending in said first single crystalline single relaxed SiGe layer.
Claim 22
Dependent Claim
35 words
The semiconductor structure of claim 20 wherein said at least one semiconductor device is a field effect transistor comprising an n-type MODFET, a p-type MODFET, a pMOS, an nMOS, a CMOS, or a combination thereof.
Claim 23
Dependent Claim
31 words
The semiconductor structure of claim 17 further comprising at least one semiconductor device formed in said pseudomorphic layer of strained single crystalline Si and optionally extending in said homo-epitaxial SiGe layer.
Claim 24
Dependent Claim
35 words
The semiconductor structure of claim 22 wherein said at least one semiconductor device is a field effect transistor comprising an n-type MODFET, a p-type MODFET, a pMOS, an nMOS, a CMOS, or a combination thereof.
Claim 25
Dependent Claim
109 words
The semiconductor structure of claim 22 further comprising a layer of single crystalline p+ doped, relaxed SiGe layer having the same composition as that of the single crystalline relaxed SiGe layer formed atop said single crystalline SiGe layer, a single crystalline SiGe layer of same composition present atop said p+ doped, relaxed SiGe layer, a pseudomorphic layer of consisting strained single crystalline SiGe formed on said single crystalline, relaxed SiGe layer, a single crystalline SiGe layer and having the same composition as p+ doped relaxed SiGe layer formed atop said pseudomorphic compressively strained SiGe layer, and a pseudomorphic Si cap layer formed atop said strained single crystalline Si layer.
Claim 26
Dependent Claim
104 words
An integrated circuit comprising: a Si substrate having a top surface; a first insulating layer atop of said Si substrate; an intermediate layer comprising a single crystalline relaxed SiGe layer of graded composition; a first single crystalline relaxed SiGe layer atop said intermediate layer, wherein said first single crystalline relaxed SiGe layer has a uniform composition, is less than 200 nm thick, and has a threading dislocation density of less than about 10 7 cm −2 ; a layer of strained single crystalline Si grown pseudomorphically on said first single crystalline relaxed SiGe layer; and at least one semiconductor device built in said layers.
Claim 27
Dependent Claim
104 words
An integrated circuit comprising: a Si substrate having a top surface; a first insulating layer atop of said Si substrate; an intermediate layer comprising a single crystalline relaxed SiGe layer of graded composition; a first single crystalline relaxed SiGe layer atop said intermediate layer, wherein said first single crystalline relaxed SiGe layer has a uniform composition, is less than 200 nm thick, and has a threading dislocation density of less than about 10 7 cm −2 ; a layer of strained single crystalline Si grown pseudomorphically on said first single crystalline relaxed SiGe layer; and at least one semiconductor device built in said layers.
Claim 28
Dependent Claim
146 words
An integrated circuit comprising: a Si substrate having a top surface; a first insulating layer atop of said substrate; a first intermediate layer comprising a single crystalline relaxed SiGe layer of graded composition; a first single crystalline relaxed SiGe layer atop said intermediate layer, wherein said first single crystalline relaxed SiGe layer has a uniform composition, is less than 200 nm thick, and has a threading dislocation density of less than about 10 7 cm −2 ; a pseudomorphic tensile strained Si layer formed atop said first single crystalline SiGe layer; a second single crystalline SiGe layer of same composition as said first SiGe layer formed atop said pseudomorphic tensile strained Si layer; a n+ doped relaxed SiGe layer formed atop said second SiGe layer; a pseudomorhic Si cap formed atop said n+ doped SiGe layer; and at least one semiconductor device built in said layers.
Claim 29
Dependent Claim
146 words
An integrated circuit comprising: a Si substrate having a top surface; a first insulating layer atop of said substrate; a first intermediate layer comprising a single crystalline relaxed SiGe layer of graded composition; a first single crystalline relaxed SiGe layer atop said intermediate layer, wherein said first single crystalline relaxed SiGe layer has a uniform composition, is less than 200 nm thick, and has a threading dislocation density of less than about 10 7 cm −2 ; a pseudomorphic tensile strained Si layer formed atop said first single crystalline SiGe layer; a second single crystalline SiGe layer of same composition as said first SiGe layer formed atop said pseudomorphic tensile strained Si layer; a n+ doped relaxed SiGe layer formed atop said second SiGe layer; a pseudomorhic Si cap formed atop said n+ doped SiGe layer; and at least one semiconductor device built in said layers.
Claim 30
Dependent Claim
165 words
An integrated circuit comprising: a Si substrate having a top surface; a first insulating layer atop of said substrate; a first intermediate layer comprising a single crystalline relaxed SiGe layer of graded composition; a first single crystalline relaxed SiGe layer atop said intermediate layer, wherein said first single crystalline relaxed SiGe layer has a uniform composition, is less than 200 nm thick, and has a threading dislocation density of less than about 10 7 cm −2 ; a single crystalline p+ doped homo-epitaxial relaxed SiGe layer formed atop said first single crystalline SiGe layer; a single crystalline relaxed SiGe layer formed atop said single crystalline p+ doped homo-epitaxial SiGe layer; a compressively strained pseudomorphic single crystalline SiGe layer formed on said homo-epitaxial single crystalline SiGe layer; a single crystalline SiGe layer formed on said compressively strained single crystalline SiGe layer; a layer of strained single crystalline Si grown pseudomorphically on said single crystalline Si layer; and at least one semiconductor device built in said layers.
Claim 31
Dependent Claim
165 words
An integrated circuit comprising: a Si substrate having a top surface; a first insulating layer atop of said substrate; a first intermediate layer comprising a single crystalline relaxed SiGe layer of graded composition; a first single crystalline relaxed SiGe layer atop said intermediate layer, wherein said first single crystalline relaxed SiGe layer has a uniform composition, is less than 200 nm thick, and has a threading dislocation density of less than about 10 7 cm −2 ; a single crystalline p+ doped homo-epitaxial relaxed SiGe layer formed atop said first single crystalline SiGe layer; a single crystalline relaxed SiGe layer formed atop said single crystalline p+ doped homo-epitaxial SiGe layer; a compressively strained pseudomorphic single crystalline SiGe layer formed on said homo-epitaxial single crystalline SiGe layer; a single crystalline SiGe layer formed on said compressively strained single crystalline SiGe layer; a layer of strained single crystalline Si grown pseudomorphically on said single crystalline Si layer; and at least one semiconductor device built in said layers.
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