US6513149B1 — Routing balanced clock signals

Claim 1

Independent Claim 139 words

A method of routing clock signals to clock loads on a circuit layout comprising the steps of: generating local clock distribution networks in defined regions of a circuit layout, each network including a local clock buffer; generating global clock distribution networks connecting the local clock buffers to a clock source with conductors of approximately equal lengths; the step of generating local clock distribution networks including steps of: grouping clock loads within the circuit layout into regions; defining conductors of the networks to connect clock loads of each region to a local clock buffer; calculating a maximum circuit parameter based on electromigration rules of metal wire layers; entering data representing each clock load within a region into an array; and processing array data after entering data for each clock load to ascertain whether the maximum circuit parameter has been exceeded.

Claim 2

Independent Claim 139 words

A method of routing clock signals to clock loads on a circuit layout comprising the steps of: generating local clock distribution networks in defined regions of a circuit layout, each network including a local clock buffer; generating global clock distribution networks connecting the local clock buffers to a clock source with conductors of approximately equal lengths; the step of generating local clock distribution networks including steps of: grouping clock loads within the circuit layout into regions; defining conductors of the networks to connect clock loads of each region to a local clock buffer; calculating a maximum circuit parameter based on electromigration rules of metal wire layers; entering data representing each clock load within a region into an array; and processing array data after entering data for each clock load to ascertain whether the maximum circuit parameter has been exceeded.

Claim 3

Dependent Claim 35 words

The method of claim 1 further including a further step of: rearranging regions including numbers of clock loads which cause the maximum circuit parameter to be exceeded until the maximum circuit parameters are not exceeded.

Claim 4

Dependent Claim 27 words

The method of claim 1 wherein said defining step includes the additional step of: determining a total length of conductor paths within each region as substantially minimum.

Claim 5

Dependent Claim 21 words

The method of claim 3 including the step of: placing on each conductor path within a region a local clock buffer.

Claim 6

Dependent Claim 141 words

A machine implemented process for routing clock signals in circuit layouts to minimize clock skew comprising the steps of: designating a path of conductors between clock loads in regions of the circuit layout to couple clocked circuit elements to a local clock buffer;. specifying a path of conductors to couple global clock buffers to the local clock buffers; the designating step including steps of: defining bounded areas enclosing all the clocked elements in the circuit; dividing a bounded area into rows of regions; positioning local clock buffers within each region; the positioning step including steps of calculating minimum length paths for successive local clock buffers; determining whether a path connecting a plurality of clocked circuit elements exceeds predetermined parameters; and continuing to add successive clocked circuit elements to a local clock buffer so long as the predetermined parameters are not exceeded.

Claim 7

Dependent Claim 141 words

A machine implemented process for routing clock signals in circuit layouts to minimize clock skew comprising the steps of: designating a path of conductors between clock loads in regions of the circuit layout to couple clocked circuit elements to a local clock buffer;. specifying a path of conductors to couple global clock buffers to the local clock buffers; the designating step including steps of: defining bounded areas enclosing all the clocked elements in the circuit; dividing a bounded area into rows of regions; positioning local clock buffers within each region; the positioning step including steps of calculating minimum length paths for successive local clock buffers; determining whether a path connecting a plurality of clocked circuit elements exceeds predetermined parameters; and continuing to add successive clocked circuit elements to a local clock buffer so long as the predetermined parameters are not exceeded.

Claim 8

Dependent Claim 43 words

The machine implemented process of claim 5 wherein the specifying steps includes steps of: defining paths of conductors coupling global clock buffers in serial fashion; and positioning global clock buffers so that the lengths of paths of conductors coupling them are approximately constant.

Claim 9

Dependent Claim 26 words

The machine implemented process of claim 6 including an initial step of: locating a first global clock buffer in approximately the center of a bounded area.

Claim 10

Dependent Claim 30 words

The machine implemented process of claim 7 including steps of: assessing power requirements of a global clock buffer when positioned; and re-executing the designating step if power requirements are excessive.

Claim 11

Dependent Claim 24 words

The machine implemented process of claim 8 wherein the re-executing step includes a step of: reducing the number of regions in the dividing step.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2006-01-27	2006-07-29	2007-01-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2010-01-27	2010-07-29	2011-01-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2014-01-27	2014-07-29	2015-01-28	$7700.00	Window Closed / Lapsed

Routing balanced clock signals

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