US6512408B2
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Mixer structure and method for using same
Assignee: GCT Semiconductor Inc
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Filing: 2001-11-06
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Granted: 2003-01-28
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Expires: 2021-11-06
Abstract
Abstract A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.
Inventors
- 👤 Kyeongho Lee
- 👤 Deog-Kyoon Jeong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:32
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/38; H04B1/40; H03; H03D; H03D7/00; H03D7/14; H03D7/1425; H03D7/1441; H03H; H03H11/00; H03H11/02; H03H11/16; H03H11/22; H03K; H03K9/00; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/16; H03L7/18; H03L7/197; H03L7/1974; H04B1/06; H04B1/16; H04B1/26; H04B1/28; H04B1/403; H03F; H03F2200/00; H03F2200/372; H03H11/04; H03H2011/0494; H03L7/085; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
77 words
A circuit, comprising: a multi-phase mixer that receives a plurality of first clock signals having different phases, each first clock signal having a first frequency which is less than a second frequency, wherein the multi-phase mixer combines the plurality of first clock signals to generate a plurality of local oscillator signals having the second frequency, and wherein the multi-phase mixer multiplies the plurality of local oscillator signals with input signals to provide output signals at output terminals.
Claim 2
Dependent Claim
77 words
A circuit, comprising: a multi-phase mixer that receives a plurality of first clock signals having different phases, each first clock signal having a first frequency which is less than a second frequency, wherein the multi-phase mixer combines the plurality of first clock signals to generate a plurality of local oscillator signals having the second frequency, and wherein the multi-phase mixer multiplies the plurality of local oscillator signals with input signals to provide output signals at output terminals.
Claim 3
Dependent Claim
49 words
The circuit of claim 1 , wherein the input signals include an I-channel signal and a Q-channel signal, and wherein the multi-phase mixer multiplies the I-channel with one of the plurality of local oscillator signals and multiplies the Q-channel signal with another of the plurality of local oscillator signals.
Claim 4
Dependent Claim
62 words
The circuit of claim 1 , further comprising a clock generator that receives a reference signal having a reference frequency and generates the plurality of first clock signals, wherein the clock generator includes a plurality of delay cells coupled in series to provide the plurality of first clock signals having different phases, and wherein the input signals are at the reference frequency.
Claim 5
Dependent Claim
80 words
The circuit of claim 1 , wherein said multi-phase mixer comprises: a load circuit coupled to a first prescribed voltage; a switch array coupled to the load circuit at terminals providing the output signals, wherein the switch array receives the plurality of first clock signals from the clock generator and outputs the local oscillator signals; and an input block coupled to the switch array, wherein the input block receives the input signals and outputs corresponding signals for the switch array.
Claim 6
Dependent Claim
23 words
The circuit of claim 4 , wherein said multi-phase mixer further comprises a bias transistor between the input block and the switch array.
Claim 7
Dependent Claim
70 words
The circuit of claim 4 , wherein the load circuit comprises: first and second transistors coupled by first electrodes to the first prescribed voltage, wherein the first and second transistors have control electrodes coupled together; a first load resistor coupled between the control electrode and a second electrode of the first transistor; and a second load resistor coupled between the control electrode and a second electrode of the second transistor.
Claim 8
Dependent Claim
70 words
The circuit of claim 4 , wherein the switch array comprises: a first switch network coupled to receive a first group of the first clock signals and coupled to the load circuit to output a corresponding first local oscillator signal; and a second switch network coupled to receive a second group of the first clock signals and coupled to the load circuit to output a corresponding second local oscillator signal.
Claim 9
Dependent Claim
26 words
The circuit of claim 7 , wherein each of said first and second switch networks comprises a plurality of switches coupled to each other in parallel.
Claim 10
Dependent Claim
21 words
The circuit of claim 8 , wherein each of said plurality of switches comprises a plurality of transistors coupled in series.
Claim 11
Dependent Claim
73 words
The circuit of claim 9 , wherein each of the plurality of switches comprises: first and third transistors coupled in series between a first node and a second node; and second and fourth transistors coupled in series between the first node and the second node, wherein control electrodes of the first and fourth electrodes receive a first control signal and control electrodes of the second and third transistors receive a second control signal.
Claim 12
Dependent Claim
73 words
The circuit of claim 10 , wherein second electrodes of the first and third electrodes are coupled together, wherein first electrodes of the first and second transistors are coupled to the first node, wherein first electrodes of the third and fourth transistors are coupled together, wherein second electrodes of the second and fourth transistors are coupled together, and wherein the first and second control signals are different ones of the first clock signals.
Claim 13
Dependent Claim
49 words
The circuit of claim 8 , wherein each of the plurality of switches coupled in parallel includes first and second plurality of transistors coupled in series, wherein each of the plurality of switches receives a different pair of the plurality of first clock signals as its respective control signals.
Claim 14
Dependent Claim
51 words
The circuit of claim 4 , wherein the switch array combines the plurality of first clock signals to generate the plurality of local oscillator signals having the second frequency substantially the same as the reference frequency and, wherein the input signals have the reference frequency and the output signals are baseband.
Claim 15
Dependent Claim
38 words
The circuit of claim 1 , wherein the multi-phase mixer includes a switch array coupled to terminals providing the output signals, wherein the switch array receives the plurality of first clock signals and outputs the local oscillator signals.
Claim 16
Dependent Claim
41 words
The circuit of claim 14 , wherein the switch array includes a plurality of transistor units coupled to each other in parallel, each transistor unit receiving at least one of the plurality of first clock signals as a respective control signal.
Claim 17
Dependent Claim
26 words
The circuit of claim 4 , wherein the input block receives input voltages of the input signals and outputs corresponding current signals to the switch array.
Claim 18
Dependent Claim
44 words
The circuit of claim 16 , wherein the input block is a transistor having a gate that receives the input signals, a first electrode coupled to a second prescribed voltage and a second electrode for outputting the corresponding current signals to the switch array.
Claim 19
Dependent Claim
50 words
The circuit of claim 1 , where in the multi-phase mixer comprises: a differential amplifying circuit for receiving the input signals and outputting the output signals; and a combining circuit coupled to the differential amplifying circuit for receiving the plurality of first clock signals and outputting the local oscillator signals.
Claim 20
Independent Claim
77 words
A method for processing input signals, comprising: generating a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency of an input signal; combining the plurality of first clock signals to generate a plurality of local oscillator signals having a second frequency higher than the first frequency; and mixing the plurality of local oscillator signals with the input signal to provide an output signal.
Claim 21
Independent Claim
77 words
A method for processing input signals, comprising: generating a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency of an input signal; combining the plurality of first clock signals to generate a plurality of local oscillator signals having a second frequency higher than the first frequency; and mixing the plurality of local oscillator signals with the input signal to provide an output signal.
Claim 22
Dependent Claim
15 words
The method of claim 19 , wherein the output signal is at a baseband frequency.
References Cited (Backward Citations)
US4755774A
Cited
US5012142A
Cited
US5180994A
Cited
US5175729A
Cited
US5438591A
Cited
US5179303A
Cited
US5418815A
Cited
US5408201A
Cited
US5878087A
Cited
US5507025A
Cited
US5584062A
Cited
US5761617A
Cited
US5448772A
Cited
US5950119A
Cited
US5734970A
Cited
US5640146A
Cited
US6084905A
Cited
US5555182A
Cited
US5861773A
Cited
US5614868A
Cited
US5794119A
Cited
US5963855A
Cited
US5872810A
Cited
US5880613A
Cited
US6097768A
Cited
US5894592A
Cited
US6029059A
Cited
US5889437A
Cited
US6175279B1
Cited
US6194947B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-01-27 | 2006-07-29 | 2007-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-01-27 | 2010-07-29 | 2011-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-01-27 | 2014-07-29 | 2015-01-28 | $7700.00 | Window Closed / Lapsed |