US5894592A
Expired / Lapsed
US
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Wideband frequency synthesizer for direct conversion transceiver
Assignee: Quarterhill Inc
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Filing: 1997-04-17
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Granted: 1999-04-13
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Expires: 2017-04-17
Abstract
Abstract A wideband phase-lock loop frequency synthesizer (200) used in a radio transceiver capable of being reconfigured to operate in either a transmit, receive, or battery save mode. The wideband phase-lock loop frequency synthesizer (200) includes, a divide-by-two divider (205), quadrature detector (204), offset VCO (209) and offset mixer (207) for generating a quadrature phase modulated signal. Moreover, a programmable filter (211) is used for removing predetermined harmonic components of the offset mixed signal enabling the synthesizer to operate over a wide frequency range.
Inventors
- 👤 Daniel E. Brueske
- 👤 Gary A. Kurtzman
- 👤 Richard B. Meador
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:38
CPC Classifications
H; H03; H03C; H03C3/00; H03C3/02; H03C3/09; H03C3/0908; H03C3/0975; H03C3/0941; H03C3/0966; H04; H04B; H04B1/00; H04B1/005; H04B1/0053; H04B1/0057; H04B1/0067; H04B1/0082; H04B1/0089; H04B1/0092; H04B1/38; H04B1/40
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
203 words
A phase-lock loop (PLL) frequency synthesizer comprising: a voltage controlled oscillator (VCO) for providing a VCO signal at a predetermined frequency; a buffer for adjusting a duty cycle of the VCO signal and providing a buffered signal; a first divider for reducing the frequency of the buffered signal to provide a first divided signal; a quadrature detector for detecting the first divided signal and providing a duty cycle feedback control to the buffer; an offset VCO for providing an external means of varying the frequency of the PLL frequency synthesizer; an offset mixer for combining the first divided signal with an offset signal to produce a mixed signal; at least one intermodulation filter for removing predetermined intermodulation components of the mixed signal and providing a filtered signal; a second divider for reducing the frequency of the filtered signal; a phase detector for detecting a phase difference between a reference signal and the filtered signal and providing a phase difference signal proportional thereto; a loop filter for filtering unwanted components from the phase difference signal; a phase modulator for providing low frequency modulation of the PLL frequency synthesizer; and a transmit stage for dividing and providing a buffered signal to a transmit power amplifier.
Claim 2
Dependent Claim
203 words
A phase-lock loop (PLL) frequency synthesizer comprising: a voltage controlled oscillator (VCO) for providing a VCO signal at a predetermined frequency; a buffer for adjusting a duty cycle of the VCO signal and providing a buffered signal; a first divider for reducing the frequency of the buffered signal to provide a first divided signal; a quadrature detector for detecting the first divided signal and providing a duty cycle feedback control to the buffer; an offset VCO for providing an external means of varying the frequency of the PLL frequency synthesizer; an offset mixer for combining the first divided signal with an offset signal to produce a mixed signal; at least one intermodulation filter for removing predetermined intermodulation components of the mixed signal and providing a filtered signal; a second divider for reducing the frequency of the filtered signal; a phase detector for detecting a phase difference between a reference signal and the filtered signal and providing a phase difference signal proportional thereto; a loop filter for filtering unwanted components from the phase difference signal; a phase modulator for providing low frequency modulation of the PLL frequency synthesizer; and a transmit stage for dividing and providing a buffered signal to a transmit power amplifier.
Claim 3
Dependent Claim
17 words
A PLL frequency synthesizer as in claim 1 wherein the phase detector includes at least one integrator.
Claim 4
Dependent Claim
17 words
A PLL frequency synthesizer as in claim 1 wherein the loop filter determines a PLL system type.
Claim 5
Dependent Claim
18 words
A PLL frequency synthesizer as in claim 1 operates in either a receive, transmit or battery save mode.
Claim 6
Dependent Claim
28 words
A PLL frequency synthesizer as in claim 1 wherein the at least one intermodulation filter operates automatically for adjusting a cutoff frequency for wideband radio frequency (RF) operation.
Claim 7
Dependent Claim
33 words
A PLL frequency synthesizer as in claim 1 wherein the offset mixer may be reconfigured as a buffer stage to reduce spurious emissions when the PLL frequency synthesizer operates in a transmit mode.
Claim 8
Dependent Claim
36 words
A PLL frequency synthesizer as in claim 1 wherein the VCO operates at a frequency that is twice the transmission frequency of the PLL frequency synthesizer for improving isolation between the VCO and the transmitted signal.
Claim 9
Dependent Claim
102 words
A wideband phase-lock loop frequency synthesizer comprising: a voltage controlled oscillator for generating a radio frequency (RF) signal; an offset mixer for combining the RF signal and an offset signal to produce a mixed signal; an intermodulation filter for eliminating unwanted intermodulation components of the mixed signal and providing a filtered signal; a divider for reducing the frequency of the filtered signal; a phase detector for altering the phase of the filtered signal and providing a phase altered signal; and a loop filter for removing spurious components of the phase altered signal and providing a feedback signal to the voltage controlled oscillator.
Claim 10
Dependent Claim
102 words
A wideband phase-lock loop frequency synthesizer comprising: a voltage controlled oscillator for generating a radio frequency (RF) signal; an offset mixer for combining the RF signal and an offset signal to produce a mixed signal; an intermodulation filter for eliminating unwanted intermodulation components of the mixed signal and providing a filtered signal; a divider for reducing the frequency of the filtered signal; a phase detector for altering the phase of the filtered signal and providing a phase altered signal; and a loop filter for removing spurious components of the phase altered signal and providing a feedback signal to the voltage controlled oscillator.
Claim 11
Dependent Claim
30 words
A wideband phase-lock loop frequency synthesizer as in claim 8 wherein the offset mixer acts to cancel an unwanted image signal created from multiplied frequency sinusoids within the offset mixer.
Claim 12
Dependent Claim
28 words
A wideband phase-lock loop frequency synthesizer as in claim 8 wherein the intermodulation filter is controlled such that its cutoff frequency is dependent on a local oscillator frequency.
Claim 13
Dependent Claim
26 words
A wideband phase-lock loop frequency synthesizer as in claim 8 further comprising an offset voltage controlled oscillator for providing an offset signal having a controllable frequency.
Claim 14
Dependent Claim
35 words
A wideband phase-lock loop frequency synthesizer as in claim 8 further comprising a mode controller for reconfiguring the wideband phase-lock loop frequency synthesizer for operation in either of a transmit, receive or battery save modes.
Claim 15
Dependent Claim
159 words
A wideband phase-lock loop oscillator comprising: a voltage controlled oscillator (VCO) for providing a radio frequency (RF) signal over a substantially wide range; a first divider for reducing the frequency of the RF signal and provided a first divided signal; a quadrature detector for altering the phase of the first divided signal to provide a first and a second quadrature signal to the first divider; an offset mixer for combining the first and second quadrature signal from the quadrature detector with an offset voltage controlled oscillator signal to provide a offset mixed signal; a second divider for reducing the frequency of the offset mixed signal to provide a second divided signal; a phase detector for varying the phase of the second divided signal of the second divider and providing a detected signal; and a loop filter for removing unwanted harmonic components of the detected signal to provide a filtered signal and for supplying the filtered signal to the VCO.
Claim 16
Dependent Claim
159 words
A wideband phase-lock loop oscillator comprising: a voltage controlled oscillator (VCO) for providing a radio frequency (RF) signal over a substantially wide range; a first divider for reducing the frequency of the RF signal and provided a first divided signal; a quadrature detector for altering the phase of the first divided signal to provide a first and a second quadrature signal to the first divider; an offset mixer for combining the first and second quadrature signal from the quadrature detector with an offset voltage controlled oscillator signal to provide a offset mixed signal; a second divider for reducing the frequency of the offset mixed signal to provide a second divided signal; a phase detector for varying the phase of the second divided signal of the second divider and providing a detected signal; and a loop filter for removing unwanted harmonic components of the detected signal to provide a filtered signal and for supplying the filtered signal to the VCO.
Claim 17
Dependent Claim
26 words
A wideband phase-lock loop oscillator as in claim 13 wherein the oscillator may be reconfigured to operate in either a transmit, receive or battery save mode.
Claim 18
Dependent Claim
30 words
A wideband phase-lock loop oscillator as in claim 13 further comprising at least one intermodulation filter for automatically adjusting a cutoff frequency of the oscillator for reducing unwanted signal components.
Claim 19
Dependent Claim
30 words
A wideband phase-lock loop oscillator as in claim 13 wherein the offset mixer may be reconfigured as a buffer stage to reduce spurious emissions when used in a transmit mode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-12 | 2002-10-12 | 2003-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-12 | 2006-10-12 | 2007-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-12 | 2010-10-12 | 2011-04-13 | $7700.00 | Window Closed / Lapsed |