Patent US6510509B1 successfully refreshed from Google Patents.
US6510509B1
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Method and apparatus for high-speed network rule processing
Assignee: SWITCH ON NETWORKS
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Filing: 1999-03-29
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Granted: 2003-01-21
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Expires: 2019-03-29
Abstract
Abstract A high-speed rule processing apparatus is disclosed that may be used to implement a wide variety of rule processing tasks such as network address translation, firewall protection, quality of service, IP routing, and/or load balancing. The high-speed rule processor uses an array of compare engines that operate in parallel. Each compare engine includes memory for storing instructions and operands, an arithmetic-logic for performing comparisons, and control circuitry for interpreting the instructions and operands. The results from the array of compare engines is prioritized using a priority encoding system.
Inventors
- 👤 Vikram Chopra
- 👤 Ajay Desai
- 👤 Raghunath Iyer
- 👤 Sundar Iyer
- 👤 Moti Jiandani
- 👤 Ajit Shelat
- 👤 Navneet Yadav
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:17
CPC Classifications
H; H04; H04L; H04L69/00; H04L69/16; H04L49/00; H04L49/90; H04L69/161; H04L9/00; H04L9/40; H04L69/12
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
111 words
A method of quickly processing an incoming packet, said method comprising: distributing information from said incoming packets from a main control unit to a plurality of nanocomputers, said nanocomputers organized into groups, each of said nanocomputers comprising a set of instructions; concurrently processing said incoming packets within said nanocomputers using at least one instruction in said nanocomputers to generate an instruction outcome in each said nanocomputer; determining a group prioritized result within each nanocomputer group; determining a global prioritized result from said group prioritized result; and returning a prioritized final result to said main control unit, said prioritized final result comprising a highest priority instruction outcome from said plurality of nanocomputers.
Claim 2
Independent Claim
111 words
A method of quickly processing an incoming packet, said method comprising: distributing information from said incoming packets from a main control unit to a plurality of nanocomputers, said nanocomputers organized into groups, each of said nanocomputers comprising a set of instructions; concurrently processing said incoming packets within said nanocomputers using at least one instruction in said nanocomputers to generate an instruction outcome in each said nanocomputer; determining a group prioritized result within each nanocomputer group; determining a global prioritized result from said group prioritized result; and returning a prioritized final result to said main control unit, said prioritized final result comprising a highest priority instruction outcome from said plurality of nanocomputers.
Claim 3
Dependent Claim
34 words
The method as claimed in claim 1 further comprising: returning a prioritized final result to said main control unit, said prioritized final result comprising a highest priority instruction outcome from said plurality of nanocomputers.
Claim 4
Dependent Claim
18 words
The method as claimed in claim 1 wherein said groups of nanocomputers her comprise a group control unit.
Claim 5
Dependent Claim
30 words
The method as claimed in claim 3 wherein adjacent nanocomputers in a nanocomputers group may be linked such that instructions in adjacent nanocomputers may be treated as a single instruction.
Claim 6
Dependent Claim
17 words
The method as claimed in claim 3 wherein said group control unit determines said group prioritized result.
Claim 7
Dependent Claim
25 words
The method as claimed in claim 5 wherein said group control unit determines said group prioritized result by polling nanocomputers in said group of nanocomputers.
Claim 8
Dependent Claim
15 words
The method as claimed in claim 1 wherein each nanocomputer comprises an arithmetic logic unit.
Claim 9
Dependent Claim
13 words
The method as claimed in claim 1 wherein each nanocomputer comprises am memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-01-20 | 2006-07-22 | 2007-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-01-20 | 2010-07-22 | 2011-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-01-20 | 2014-07-22 | 2015-01-21 | $7700.00 | Window Closed / Lapsed |