Patent US6507931B2 successfully refreshed from Google Patents.
US6507931B2
Expired / Lapsed
US
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Semiconductor integrated circuit designing method and system
Assignee: Toshiba Corp
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Filing: 2001-06-28
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Granted: 2003-01-14
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Expires: 2021-06-28
Abstract
Abstract A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
Inventors
- 👤 Toshiya Kotani
- 👤 Satoshi Tanaka
- 👤 Soichi Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:25
CPC Classifications
H; H10; H10P; H10P95/00; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
96 words
A method for designing a semiconductor integrated circuit, comprising: compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern; predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern; obtaining an evaluated value by comparing the predicted pattern with the compacted pattern; deciding whether the evaluated value satisfies a predetermined condition; and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
Claim 2
Independent Claim
96 words
A method for designing a semiconductor integrated circuit, comprising: compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern; predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern; obtaining an evaluated value by comparing the predicted pattern with the compacted pattern; deciding whether the evaluated value satisfies a predetermined condition; and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
Claim 3
Dependent Claim
41 words
A method according to claim 1 , wherein the pattern formed at a surface area of a wafer is predicted using data obtained by converting data of the compacted pattern to mask data for photolithography or data for electron beam lithography.
Claim 4
Dependent Claim
109 words
A method according to claim 1 , wherein the pattern formed at a surface area of a wafer is predicted using at least one model selected from a first prediction model, second prediction model and third prediction model, the first prediction model being a model for calculating a light exposed state of a resist on the wafer when the compacted pattern is projected on the resist, the second prediction model being a model for calculating a resist pattern configuration after the resist has been developed, and the third prediction model being a model for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern.
Claim 5
Independent Claim
106 words
A system for designing a semiconductor integrated circuit, comprising: means for compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern; means for predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern; means for obtaining an evaluated value by comparing the predicted pattern with the compacted pattern; means for deciding whether the evaluated value satisfies a predetermined condition; and means for modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
Claim 6
Independent Claim
106 words
A system for designing a semiconductor integrated circuit, comprising: means for compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern; means for predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern; means for obtaining an evaluated value by comparing the predicted pattern with the compacted pattern; means for deciding whether the evaluated value satisfies a predetermined condition; and means for modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
Claim 7
Dependent Claim
41 words
A system according to claim 4 , wherein the pattern formed at a surface area of a wafer is predicted using data obtained by converting data of the compacted pattern to mask data for lithography or data for electron beam lithography.
Claim 8
Dependent Claim
109 words
A system according to claim 4 , wherein the pattern formed at a surface area of a wafer is predicted using at least one model selected from a first prediction model, second prediction model and third prediction model, the first prediction model being a model for calculating a light exposed state of a resist on the wafer when the compacted pattern is projected on the resist, the second prediction model being a model for calculating a resist pattern configuration after the resist has been developed, and the third prediction model being a model for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern.
Claim 9
Dependent Claim
117 words
A computer readable medium configured to store program instructions for causing a computer to compact a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, causing the computer to predict a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, causing the computer to obtain an evaluated value by comparing the predicted pattern with the compacted pattern, causing the computer to decide whether the evaluated value satisfies a predetermined condition, and causing the computer to modify the design rule when the evaluated value is decided as not satisfying the predetermined condition.
Claim 10
Dependent Claim
117 words
A computer readable medium configured to store program instructions for causing a computer to compact a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, causing the computer to predict a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, causing the computer to obtain an evaluated value by comparing the predicted pattern with the compacted pattern, causing the computer to decide whether the evaluated value satisfies a predetermined condition, and causing the computer to modify the design rule when the evaluated value is decided as not satisfying the predetermined condition.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-01-13 | 2006-07-15 | 2007-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-01-13 | 2010-07-15 | 2011-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-01-13 | 2014-07-15 | 2015-01-14 | $7700.00 | Window Closed / Lapsed |