Feedback clamp circuit to prevent overcharge in compensation capacitor

Claim 2

A dual stage amplifier, comprising: a first amplifier stage having a first stage input and a first stage output; a second amplifier stage having a second stage input operatively connected to the first stage output, and a second stage output; a compensation capacitor in electrical communication with the second stage input and the second stage output; and a clamping circuit in electrical communication with the second stage, and adapted to prevent an overcharging of the compensation capacitor when an imbalance condition exists at the first stage input of the first amplifier stage.

Claim 3

The amplifier of claim 1 , wherein the clamping circuit includes a low vgs clamp adapted to bias the second stage input away from a negative supply when a voltage at the second stage input falls below a first predetermined level.

Claim 4

The amplifier of claim 2 , wherein the low vgs clamp is further adapted to sense a voltage drop below the first predetermined level at the second stage input and to inject current from a positive supply into the second stage input to counteract the sensed voltage drop, whereby the second stage input is biased away from the negative supply in response thereto.

Claim 5

The amplifier of claim 3 , wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the low vgs clamp comprises a first switching component operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and a second switching component operatively connected to the positive supply and the first switching component, and adapted to selectively provide current to the gate of the MOS output transistor according to the signal from the first switching component, whereby the current provided to the gate of the MOS output transistor counteracts a voltage drop at the second stage input.

Claim 6

The amplifier of claim 2 , wherein the clamping circuit includes a high vgs clamp adapted to bias the second stage input away from a positive supply when a voltage at the second stage input rises above a second predetermined level.

Claim 7

The amplifier of claim 5 , wherein the high vgs clamp is further adapted to sense a voltage rise above the second predetermined level at the second stage input and to sink current to the negative supply from the second stage input to counteract the sensed voltage rise, whereby the second stage input is biased away from the positive supply in response thereto.

Claim 8

The amplifier of claim 6 , wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the high vgs clamp comprises a first switching component operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and a second switching component operatively connected to the negative supply and the first switching component and adapted to selectively sink current from the gate of the MOS output transistor according to the signal from the first switching component, whereby the current sinked from the gate of the MOS output transistor counteracts a voltage rise at the second stage input.

Claim 9

The amplifier of claim 7 , wherein the high vgs clamp is further adapted to sense a voltage rise at the second stage input and to sink current to a negative supply from the second stage input to counteract the sensed voltage rise, whereby the second stage input is biased away from the positive supply in response thereto.

Claim 10

The amplifier of claim 8 , wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the high vgs clamp comprises a first switching component operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and a second switching component operatively connected to the negative supply and the first switching component and adapted to selectively sink current from the gate of the MOS output transistor according to the signal from the first switching component, whereby the current sinked from the gate of the MOS output transistor counteracts a voltage rise at the second stage input.

Claim 11

The amplifier of claim 1 , wherein the clamping circuit includes a high vgs clamp adapted to bias the second stage input away from a positive supply when a voltage at the second stage input rises above a predetermined level.

Claim 12

A clamp circuit for clamping an input in a dual stage amplifier having a first amplifier stage with a first stage input and a first stage output and a second amplifier stage with a second stage input operatively connected to the first stage output, and a second stage output, the clamp circuit comprising: a circuit for sensing a voltage at the second stage input and providing a signal according to the sensed voltage; and a circuit for selectively sourcing or sinking current to the second stage input according to the signal, wherein the circuit for sensing a voltage at the second stage input and providing a signal according to the sensed voltage comprises a first switching component operatively connected to the second stage input and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and wherein the circuit for selectively sourcing or sinking current to the second stage input according to the signal comprises a second switching component operatively connected the first-switching component and one of a positive and a negative supply, and adapted to selectively source or sink current to or from the second stage input, respectively, according to the signal from the first switching component.

Claim 13

A clamp circuit for clamping an input in a dual stage amplifier having a first amplifier stage with a first stage input and a first stage output and a second amplifier stage with a second stage input operatively connected to the first stage output, and a second stage output, the clamp circuit comprising: a circuit for sensing a voltage at the second stage input and providing a signal according to the sensed voltage; and a circuit for selectively sourcing or sinking current to the second stage input according to the signal, wherein the circuit for sensing a voltage at the second stage input and providing a signal according to the sensed voltage comprises a first switching component operatively connected to the second stage input and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and wherein the circuit for selectively sourcing or sinking current to the second stage input according to the signal comprises a second switching component operatively connected the first-switching component and one of a positive and a negative supply, and adapted to selectively source or sink current to or from the second stage input, respectively, according to the signal from the first switching component.

Claim 14

The clamp circuit of claim 11 , wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the first switching component is operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and wherein the second switching component is operatively connected to a positive supply and the first switching component and adapted to selectively provide current to the gate of the MOS output transistor according to the signal from the first switching component, whereby the current provided to the gate of the MOS output transistor counteracts a voltage drop at the second stage input.

Claim 15

The clamp circuit of claim 11 , wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the first switching component is operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and wherein the second switching component is operatively connected to a negative supply and the first switching component and adapted to selectively sink current from the gate of the MOS output transistor according to the signal from the first switching component, whereby the current sinked from the gate of the MOS output transistor counteracts a voltage rise at the second stage input.

Claim 16

In a dual stage amplifier having a first amplifier stage with a first stage input and a first stage output and a second amplifier stage with a second stage input operatively connected to the first stage output, and a second stage output, a method of biasing the second stage input, comprising: providing a first component in electrical communication with the second stage input; sensing a voltage at the second stage input using the first component; generating a signal using the first component according to the sensed voltage at the second stage input; providing a second component in electrical communication with the first component and the second stage input; and selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component.

Claim 17

In a dual stage amplifier having a first amplifier stage with a first stage input and a first stage output and a second amplifier stage with a second stage input operatively connected to the first stage output, and a second stage output, a method of biasing the second stage input, comprising: providing a first component in electrical communication with the second stage input; sensing a voltage at the second stage input using the first component; generating a signal using the first component according to the sensed voltage at the second stage input; providing a second component in electrical communication with the first component and the second stage input; and selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component.

Claim 18

The method of claim 14 , wherein selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component comprises selectively sourcing or sinking current to or from the second stage input, respectively, using the second component according to the signal from the first component.

Claim 19

The method of claim 15 , wherein selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component comprises selectively sourcing current to the second stage input using the second component according to the signal from the first component, whereby the second stage input is selectively biased away from the negative supply.

Claim 20

The method of claim 16 , wherein selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component comprises selectively sinking current from the second stage input using the second component according to the signal from the first component, whereby the second stage input is selectively biased away from the positive supply.

Claim 21

The method of claim 15 , wherein selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component comprises selectively sinking current from the second stage input using the second component according to the signal from the first component, whereby the second stage input is selectively biased away from the positive supply.

Claim 22

The method of claim 14 , wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the first component is operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and wherein the second component is operatively connected to the positive supply and the first switching component and adapted to selectively source or sink current to or from the gate of the MOS output transistor, respectively, according to the signal from the first switching component, whereby the current sourced to or sinked from the gate of the MOS output transistor counteracts a voltage change at the second stage input.