Patent US6502162B2 successfully refreshed from Google Patents.
US6502162B2
Expired / Lapsed
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Configuring vectors of logical storage units for data storage partitioning and sharing
Assignee: EMC Corp
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Filing: 2001-07-06
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Granted: 2002-12-31
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Expires: 2021-07-06
Abstract
Abstract In a data storage subsystem providing data storage to host processors, a process of configuration defines a subset of the data storage that each host may access. A vector specification is a convenient mechanism for specifying a set of storage volumes that a host may access. For example, for each host processor, there is stored in memory of the data storage subsystem a list of contiguous ranges or vectors of the storage volumes that the host may access. To determine whether or not a specified logical volume number is included in the vector, a mudulus of the stride of the vector is computed from the difference between the address of the specified logical volume and the beginning address of the vector, and the modulus is compared to zero. To provide a mapping between logical unit numbers specified by the host and the logical volumes, a contiguous range of logical unit numbers may also be specified for each contiguous range or vector of storage volumes. The logical volume number is computed from a specified logical unit number by computing a difference between the specified logical unit number and the beginning logical unit number, multiplying the difference by the stride of the vector to produce a product, and adding the product to the beginning address of the vector.
Inventors
- 👤 Steven M. Blumenau
- 👤 Yoav Raz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:42
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/062; G06F3/0622; G06F12/00; G06F12/02; G06F12/06; G06F12/0607; G06F3/0628; G06F3/0638; G06F3/0644; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0674
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
229 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and which includes storing the vector specification in memory of the data storage subsystem, and the vector specification stored in memory of the data storage subsystem includes a specification of the beginning address (BEGIN), a specification of the stride (S), and a specification of an ending address (END) of a last addressable logical storage unit in the series of the addressable logical storage units.
Claim 2
Independent Claim
229 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and which includes storing the vector specification in memory of the data storage subsystem, and the vector specification stored in memory of the data storage subsystem includes a specification of the beginning address (BEGIN), a specification of the stride (S), and a specification of an ending address (END) of a last addressable logical storage unit in the series of the addressable logical storage units.
Claim 3
Independent Claim
195 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and which further includes operating the data storage subsystem to compute the addresses in the vector in order to report the logical storage units that a host processor may access.
Claim 4
Independent Claim
195 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and which further includes operating the data storage subsystem to compute the addresses in the vector in order to report the logical storage units that a host processor may access.
Claim 5
Dependent Claim
43 words
The method as claimed in claim 2 , wherein the data storage subsystem computes the addresses in the vector in response to a request from the host processor for a report of the logical storage units that are accessible to the host processor.
Claim 6
Dependent Claim
33 words
The method as claimed in claim 2 , wherein the data storage subsystem reports to a system administrator at a graphical user interface the logical storage units that the host processor may access.
Claim 7
Independent Claim
286 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising; a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and which further includes the data storage subsystem determining whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor, in order to grant the host processor access to a logical storage unit having the specified address when the specified address is within the vector of addresses of logical storage units that have been configured for access by the host processor, and to deny the host processor access to a logical storage unit having the specified address when the specified address is not within the vector of logical storage units that have been configured for access by the host processor.
Claim 8
Independent Claim
286 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising; a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and which further includes the data storage subsystem determining whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor, in order to grant the host processor access to a logical storage unit having the specified address when the specified address is within the vector of addresses of logical storage units that have been configured for access by the host processor, and to deny the host processor access to a logical storage unit having the specified address when the specified address is not within the vector of logical storage units that have been configured for access by the host processor.
Claim 9
Independent Claim
251 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and which includes assigning a range of contiguous logical unit numbers used by a host processor to the vector specification of a series of the addressable logical storage units to establish a mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units, and storing in memory a specification of the mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units.
Claim 10
Independent Claim
251 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and which includes assigning a range of contiguous logical unit numbers used by a host processor to the vector specification of a series of the addressable logical storage units to establish a mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units, and storing in memory a specification of the mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units.
Claim 11
Dependent Claim
104 words
The method as claimed in claim 6 , wherein the data storage subsystem responds to a request from the host processor for access to a specified logical unit number by checking whether or not the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, and when the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, computing an address of a logical storage unit from the specified logical unit number, and accessing the logical storage unit having the address computed from the specified logical unit number.
Claim 12
Independent Claim
233 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the vector represents addresses of logical storage units, each of said logical storage units is accessible to a respective different host processor that has access to no other logical storage unit having an address represented by the vector, and said each of said logical storage units is accessible to another host processor having access to all of the logical storage units having addresses represented by the vector.
Claim 13
Independent Claim
233 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the vector represents addresses of logical storage units, each of said logical storage units is accessible to a respective different host processor that has access to no other logical storage unit having an address represented by the vector, and said each of said logical storage units is accessible to another host processor having access to all of the logical storage units having addresses represented by the vector.
Claim 14
Independent Claim
228 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2, . . . , and wherein the stride (S) is a non-zero integer different from one; and wherein the assigning includes storing in memory of the data storage subsystem a specification of the logical storage units that said each host processor may access, the specification of the logical storage units that said each host processor may access including a list of contiguous ranges or vectors of addresses of the logical storage units that said each host processor may access.
Claim 15
Independent Claim
228 words
A method of configuring data storage in a data storage subsystem for restricting access of host processors to the data storage, said method comprising: a) subdividing the data storage into addressable logical storage units; and b) assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted; wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2, . . . , and wherein the stride (S) is a non-zero integer different from one; and wherein the assigning includes storing in memory of the data storage subsystem a specification of the logical storage units that said each host processor may access, the specification of the logical storage units that said each host processor may access including a list of contiguous ranges or vectors of addresses of the logical storage units that said each host processor may access.
Claim 16
Dependent Claim
93 words
The method as claimed in claim 9 , wherein the assigning further includes storing in memory of the data storage subsystem a respective specification of a contiguous range of logical unit numbers that said each host processor may specify for each of the contiguous ranges or vectors of address of the logical storage units that said each host processor may access, so that a mapping is established between the logical unit numbers specified by said each host processor and the addresses of the logical storage units that said each host processor may access.
Claim 17
Dependent Claim
215 words
A data storage subsystem comprising, in combination: data storage; and a storage controller coupled to the data storage for controlling access to the data storage, the storage controller having at least one data port for linking the data storage to a plurality of host processors for transfer of data between the data storage and the host processors, wherein the storage controller is programmed to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one.
Claim 18
Dependent Claim
215 words
A data storage subsystem comprising, in combination: data storage; and a storage controller coupled to the data storage for controlling access to the data storage, the storage controller having at least one data port for linking the data storage to a plurality of host processors for transfer of data between the data storage and the host processors, wherein the storage controller is programmed to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one.
Claim 19
Dependent Claim
78 words
The data storage subsystem as claimed in claim 11 , wherein the storage controller is programmed to store the vector specification in memory of the data storage subsystem, wherein the vector specification stored in memory of the data storage subsystem includes a specification of the beginning address (BEGIN), a specification of the stride (S), and a specification of an ending address (END) of a last addressable logical storage unit in the series of the addressable logical storage units.
Claim 20
Dependent Claim
37 words
The data storage subsystem as claimed in claim 11 , wherein the storage controller is programmed to compute the addresses in the vector in order to report the logical storage units that a host processor may access.
Claim 21
Dependent Claim
47 words
The data storage subsystem as claimed in claim 13 , wherein the storage controller is programmed to compute the addresses in the vector in response to a request from the host processor for a report of the logical storage units that are accessible to the host processor.
Claim 22
Dependent Claim
38 words
The data storage subsystem as claimed in claim 13 , wherein the data storage subsystem is programmed to report to a system administrator at a graphical user interface the logical storage units that the host processor may access.
Claim 23
Dependent Claim
130 words
The data storage subsystem as claimed in claim 11 , wherein the storage controller is programmed to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor, in order to grant the host processor access to a logical storage unit having the specified address when the specified address is within the vector of addresses of logical storage units that have been configured for access by the host processor, and to deny the host processor access to a logical storage unit having the specified address when the specified address is not within the vector of logical storage units that have been configured for access by the host processor.
Claim 24
Dependent Claim
106 words
The data storage subsystem as claimed in claim 11 , wherein the storage controller is programmed to assign a range of contiguous logical unit numbers used by a host processor to the vector specification of a series of the addressable logical storage units to establish a mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units, and to store in memory of the data storage subsystem a specification of the mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units.
Claim 25
Dependent Claim
108 words
The data storage subsystem as claimed in claim 17 , wherein the storage controller is programmed to respond to a request from the host processor for access to a specified logical unit number by checking whether or not the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, and when the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, computing an address of a logical storage unit from the specified logical unit number, and accessing the logical storage unit having the address computed from the specified logical unit number.
Claim 26
Dependent Claim
78 words
The data storage subsystem as claimed in claim 11 , wherein the vector represents addresses of logical storage units, each of said logical storage units is accessible to a respective different host processor that has access to no other logical storage unit having an address represented by the vector, and said each of said logical storage units is accessible to another host processor having access to all of the logical storage units having addresses represented by the vector.
Claim 27
Dependent Claim
76 words
The data storage subsystem as claimed in claim 11 , wherein the storage controller is programmed to store in memory of the data storage subsystem a specification of the logical storage units that said each host processor may access, wherein the specification of the logical storage units that said each host processor may access includes a list of contiguous ranges or vectors of addresses of the logical storage units that said each host processor may access.
Claim 28
Dependent Claim
98 words
The data storage subsystem as claimed in claim 20 , wherein the storage controller is further programmed to store in memory of the data storage subsystem a specification of a respective contiguous range of logical unit numbers that said each host processor may specify for each of the contiguous ranges or vectors of address of the logical storage units that said each host processor may access, so that a mapping is established between the logical unit numbers specified by said each host processor and the addresses of the logical storage units that said each host processor may access.
Claim 29
Dependent Claim
185 words
A machine-readable program storage device containing a program for a storage controller for controlling access of a plurality of host processors to data storage, wherein the program is executable by the storage controller to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one.
Claim 30
Dependent Claim
185 words
A machine-readable program storage device containing a program for a storage controller for controlling access of a plurality of host processors to data storage, wherein the program is executable by the storage controller to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one.
Claim 31
Dependent Claim
80 words
The machine-readable program storage device as claimed in claim 22 , wherein the program is executable by the storage controller to store the vector specification in memory of the storage controller, wherein the vector specification stored in memory of the storage controller includes a specification of the beginning address (BEGIN), a specification of the stride (S), and a specification of an ending address (END) of a last addressable logical storage unit in the series of the addressable logical storage units.
Claim 32
Dependent Claim
41 words
The machine-readable program storage device as claimed in claim 22 , wherein the program is executable by the storage controller to compute the addresses in the vector in order to report the logical storage units that a host processor may access.
Claim 33
Dependent Claim
51 words
The machine-readable program storage device as claimed in claim 24 , wherein the program is executable by the storage controller to compute the addresses in the vector in response to a request from the host processor for a report of the logical storage units that are accessible to the host processor.
Claim 34
Dependent Claim
41 words
The machine-readable program storage device as claimed in claim 24 , wherein the program is executable by the storage controller to report to a system administrator at a graphical user interface the logical storage units that the host processor may access.
Claim 35
Dependent Claim
134 words
The machine-readable program storage device as claimed in claim 22 , wherein the program is executable by the storage controller to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor, in order to grant the host processor access to a logical storage unit having the specified address when the specified address is within the vector of addresses of logical storage units that have been configured for access by the host processor, and to deny the host processor access to a logical storage unit having the specified address when the specified address is not within the vector of logical storage units that have been configured for access by the host processor.
Claim 36
Dependent Claim
109 words
The machine-readable program storage device as claimed in claim 22 , wherein the program is executable by the storage controller to assign a range of contiguous logical unit numbers used by a host processor to the vector specification of a series of the addressable logical storage units to establish a mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units, and to store in memory of the storage controller a specification of the mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units.
Claim 37
Dependent Claim
112 words
The machine-readable program storage device as claimed in claim 28 , wherein the program is executable by the storage controller to respond to a request from the host processor for access to a specified logical unit number by checking whether or not the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, and when the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, computing an address of a logical storage unit from the specified logical unit number, and accessing the logical storage unit having the address computed from the specified logical unit number.
Claim 38
Dependent Claim
79 words
The machine-readable program storage device as claimed in claim 22 , wherein the program is executable by the storage controller to store in memory of the storage controller a specification of the logical storage units that said each host processor may access, wherein the specification of the logical storage units that said each host processor may access includes a list of contiguous ranges or vectors of addresses of the logical storage units that said each host processor may access.
Claim 39
Dependent Claim
101 words
The machine-readable program storage device as claimed in claim 30 , wherein the program is further executable by the storage controller to store in memory of the storage controller a specification of a respective contiguous range of logical unit numbers that said each host processor may specify for each of the contiguous ranges or vectors of address of the logical storage units that said each host processor may access, so that a mapping is established between the logical unit numbers specified by said each host processor and the addresses of the logical storage units that said each host processor may access.
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USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 2005-12-30 | 2006-07-01 | 2006-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-30 | 2010-07-01 | 2010-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-30 | 2014-07-01 | 2014-12-31 | $7700.00 | Window Closed / Lapsed |