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US6498502B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Apparatus and method for evaluating semiconductor structures and devices

Assignee: Texas Instruments Inc
•
Filing: 2000-12-14
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Granted: 2002-12-24
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Expires: 2020-12-14
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Abstract

Abstract An apparatus and method for evaluating semiconductor structures and devices are provided. A method for evaluating at least one selected electrical property of a semiconductor device ( 201 ) in relation to a selected geometric dimension of the semiconductor device ( 201 ). The method further includes forming a plurality of semiconductor devices ( 201 ) on a substrate ( 202 ), the devices ( 201 ) having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices ( 201 ) using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device ( 201 ). The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.

Inventors

  • 👤 Henry L. Edwards
  • 👤 Theodore S. Moise
  • 👤 Glen D. Wilk

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 10:22
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/302; G01R31/303; G01R31/312; Y; Y10; Y10S; Y10S977/00; Y10S977/84; Y10S977/849; Y10S977/852

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 159 words
A method for evaluating properties of a semiconductor device comprising: a. forming a plurality of semiconductor devices on a semiconductor substrate, the devices having geometric dimensions, the geometric dimensions being formed according to design rules including a minimum design rule, at least one of the devices having at least one geometric dimension approximately equaling the minimum design rule; b. measuring an electrical property of the plurality of devices related to a selected geometric dimension using a scanning probe microscopy based technique, the measurement being associated with the selected geometric dimension, including the dimension approximately equaling the minimum design rule; c. determining a relationship between the measured electrical property and the selected geometric dimension of the plurality of semiconductor devices; d. determining a relationship between the measured electrical property and at least one semiconductor fabrication process; and e. evaluating the semiconductor fabrication process based on the relationship between the measured electrical property and the geometric dimension of the semiconductor devices.
Claim 2
Independent Claim 159 words
A method for evaluating properties of a semiconductor device comprising: a. forming a plurality of semiconductor devices on a semiconductor substrate, the devices having geometric dimensions, the geometric dimensions being formed according to design rules including a minimum design rule, at least one of the devices having at least one geometric dimension approximately equaling the minimum design rule; b. measuring an electrical property of the plurality of devices related to a selected geometric dimension using a scanning probe microscopy based technique, the measurement being associated with the selected geometric dimension, including the dimension approximately equaling the minimum design rule; c. determining a relationship between the measured electrical property and the selected geometric dimension of the plurality of semiconductor devices; d. determining a relationship between the measured electrical property and at least one semiconductor fabrication process; and e. evaluating the semiconductor fabrication process based on the relationship between the measured electrical property and the geometric dimension of the semiconductor devices.
Claim 3
Dependent Claim 13 words
The method in claim 1 in which the semiconductor devices are integrated capacitors.
Claim 4
Dependent Claim 18 words
The method in claim 1 in which the measured electrical properties include capacitance, leakage, conductivity, resistivity, and voltage.

References Cited (Backward Citations)

US5053699A Cited
US5426302A Cited
US5517027A Cited
US5523700A Cited
US5793051A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2005-12-23 2006-06-24 2006-12-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2009-12-23 2010-06-24 2010-12-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2013-12-23 2014-06-24 2014-12-24 $7700.00 Window Closed / Lapsed

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