US6495885B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Graded LDD implant process for sub-half-micron MOS devices
Assignee: Micron Technology Inc
•
Filing: 2000-02-16
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Granted: 2002-12-17
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Expires: 2020-02-16
Abstract
Abstract A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N− LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.
Inventors
- 👤 Aftab Ahmad
- 👤 Charles Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01354; H10D64/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S257/00; Y10S257/90; Y10S257/917
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
242 words
A MOSFET comprising: a semiconductor substrate having a surface; a source region and a drain region below said surface; a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure; a first lightly doped region located solely below the first sidewall structure and located adjacent to and substantially not extending into and under the source region; a second lightly doped region located solely below the second sidewall structure and located adjacent to and substantially not extending into and under the drain region; a first implanted region extending below the source region and the first lightly doped region; a second implanted region extending below the drain region and the second lightly doped region; a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a channel region below the gate structure and extending between the first and the second lightly doped regions; a junction between the source region and the first lightly doped region having a first grading of dopant concentration; a junction between the first lightly doped region and the channel region having a second grading of dopant concentration; a junction between the channel region and the second lightly doped region having a third grading of dopant concentration; and a junction between the second lightly doped region and the drain region having a fourth grading of dopant concentration.
Claim 2
Dependent Claim
242 words
A MOSFET comprising: a semiconductor substrate having a surface; a source region and a drain region below said surface; a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure; a first lightly doped region located solely below the first sidewall structure and located adjacent to and substantially not extending into and under the source region; a second lightly doped region located solely below the second sidewall structure and located adjacent to and substantially not extending into and under the drain region; a first implanted region extending below the source region and the first lightly doped region; a second implanted region extending below the drain region and the second lightly doped region; a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a channel region below the gate structure and extending between the first and the second lightly doped regions; a junction between the source region and the first lightly doped region having a first grading of dopant concentration; a junction between the first lightly doped region and the channel region having a second grading of dopant concentration; a junction between the channel region and the second lightly doped region having a third grading of dopant concentration; and a junction between the second lightly doped region and the drain region having a fourth grading of dopant concentration.
Claim 3
Dependent Claim
31 words
The MOSFET of claim 1 , wherein each of the first and second sidewall structures comprises a layer of oxide and an insulating layer extending solely over the layer of oxide.
Claim 4
Dependent Claim
25 words
The MOSFET of claim 1 , wherein the gate structure comprises an oxide layer, a polysilicon layer, a tungsten suicide layer and a nitride layer.
Claim 5
Dependent Claim
26 words
The MOSFET of claim 1 , wherein each of the drain region and the source region comprise a lightly doped region and a heavily doped region.
Claim 6
Dependent Claim
26 words
The MOSFET of claim 4 , wherein the lightly doped regions within each of the drain region and the source region comprise low dosage arsenic implants.
Claim 7
Dependent Claim
26 words
The MOSFET of claim 4 , wherein the heavily doped regions within each of the drain region and the source region comprise high dosage arsenic implants.
Claim 8
Dependent Claim
20 words
The MOSFET of claim 1 , wherein the first and second lightly doped regions comprise low dosage arsenic LDD regions.
Claim 9
Dependent Claim
15 words
The MOSFET of claim 1 , wherein the graded junctions comprise low dosage phosphorous implants.
Claim 10
Dependent Claim
24 words
The MOSFET of claim 1 , wherein each of the first implanted region and the second implanted region comprise a low dosage phosphorous implant.
Claim 11
Dependent Claim
22 words
The MOSFET of claim 1 , wherein each of the third implanted region and the fourth implanted region comprise a boron implant.
Claim 12
Dependent Claim
216 words
A MOSFET comprising: a semiconductor substrate having a surface; a source region and a drain region below said surface; a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure; a first lightly doped region located solely below the first sidewall structure and located adjacent to but not substantially extending into and under the source region; a second lightly doped region located solely below the second sidewall structure and located adjacent to but not substantially extending into and under the drain region; a first implanted region extending below the source region and the first lightly doped region; a second implanted region extending below the drain region and the second lightly doped region; a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a channel region below the gate structure and extending between the first and the second lightly doped regions; and a plurality of junctions between each of the source region and the first lightly doped region, the first lightly doped region and the channel, the channel and the second lightly doped region and the second lightly doped region and the drain region, each junction including a grading of dopant concentration.
Claim 13
Dependent Claim
216 words
A MOSFET comprising: a semiconductor substrate having a surface; a source region and a drain region below said surface; a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure; a first lightly doped region located solely below the first sidewall structure and located adjacent to but not substantially extending into and under the source region; a second lightly doped region located solely below the second sidewall structure and located adjacent to but not substantially extending into and under the drain region; a first implanted region extending below the source region and the first lightly doped region; a second implanted region extending below the drain region and the second lightly doped region; a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a channel region below the gate structure and extending between the first and the second lightly doped regions; and a plurality of junctions between each of the source region and the first lightly doped region, the first lightly doped region and the channel, the channel and the second lightly doped region and the second lightly doped region and the drain region, each junction including a grading of dopant concentration.
Claim 14
Dependent Claim
20 words
The MOSFET of claim 11 , wherein the first and second lightly doped regions comprise low dosage arsenic LDD regions.
Claim 15
Dependent Claim
15 words
The MOSFET of claim 11 , wherein the graded junctions comprise low dosage phosphorous implants.
Claim 16
Dependent Claim
154 words
A MOSFET on a semiconductor substrate having a source region and a drain region, the MOSFET comprising: at least one lightly doped region located adjacent at least one of the source region and the drain region but not substantially extending thereinto and thereunder; a first implanted region extending below the source region; a second implanted region extending below the drain region; a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a gate structure; a channel region below the gate structure and abutting the at least one lightly doped region; a first grading of dopant concentration across a junction between the at least one lightly doped region and the at least one of the source region and the drain region; and a second grading of dopant concentration across a junction between the at least one lightly doped region and the channel region.
Claim 17
Dependent Claim
154 words
A MOSFET on a semiconductor substrate having a source region and a drain region, the MOSFET comprising: at least one lightly doped region located adjacent at least one of the source region and the drain region but not substantially extending thereinto and thereunder; a first implanted region extending below the source region; a second implanted region extending below the drain region; a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a gate structure; a channel region below the gate structure and abutting the at least one lightly doped region; a first grading of dopant concentration across a junction between the at least one lightly doped region and the at least one of the source region and the drain region; and a second grading of dopant concentration across a junction between the at least one lightly doped region and the channel region.
Claim 18
Dependent Claim
21 words
The MOSFET of claim 14 , wherein the at least one lightly doped region comprises a low dosage arsenic LDD region.
Claim 19
Dependent Claim
16 words
The MOSFET of claim 14 , wherein the first grading comprises a low dosage phosphorous implant.
Claim 20
Dependent Claim
16 words
The MOSFET of claim 14 , wherein the second grading comprises a low dosage phosphorous implant.
Claim 21
Dependent Claim
29 words
The MOSFET of claim 14 , wherein the at least one of the source region and the drain region comprises a heavily doped region and a lightly doped region.
Claim 22
Dependent Claim
30 words
The MOSFET of claim 18 , wherein the lightly doped region of the at least one of the source region and the drain region comprises a low dosage arsenic implant.
Claim 23
Dependent Claim
30 words
The MOSFET of claim 18 , wherein the heavily doped region of the at least one of the source region and the drain region comprises a high dosage arsenic implant.
Claim 24
Dependent Claim
197 words
A MOSFET comprising: a semiconductor substrate having a surface; a source region and a drain region below said surface; a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure; a first doped region located solely below the first sidewall structure and located adjacent to the source region but not substantially extending thereinto and thereunder; a second doped region below the second sidewall structure and adjacent to the drain region; a first implanted region extending below the source region and the first doped region; a second implanted region extending below the drain region and the second doped region; a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a channel region below the gate structure and extending between the first and the second doped regions; and a plurality of junctions between each of the source region and the first doped region, the first doped region and the channel, the channel and the second doped region and the second doped region and the drain region, each junction including a grading of dopant concentration.
Claim 25
Dependent Claim
197 words
A MOSFET comprising: a semiconductor substrate having a surface; a source region and a drain region below said surface; a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure; a first doped region located solely below the first sidewall structure and located adjacent to the source region but not substantially extending thereinto and thereunder; a second doped region below the second sidewall structure and adjacent to the drain region; a first implanted region extending below the source region and the first doped region; a second implanted region extending below the drain region and the second doped region; a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a channel region below the gate structure and extending between the first and the second doped regions; and a plurality of junctions between each of the source region and the first doped region, the first doped region and the channel, the channel and the second doped region and the second doped region and the drain region, each junction including a grading of dopant concentration.
Claim 26
Dependent Claim
26 words
The MOSFET of claim 21 , wherein each of the drain region and the source region comprise a lightly doped region and a heavily doped region.
Claim 27
Dependent Claim
21 words
The MOSFET of claim 21 , wherein each of the first and second doped regions comprise a low dosage arsenic implant.
Claim 28
Dependent Claim
22 words
The MOSFET of claim 21 , wherein each of the drain region and the source region comprise a high dosage arsenic implant.
Claim 29
Dependent Claim
21 words
The MOSFET of claim 21 , wherein each of the first and second implanted regions comprise a low dosage phosphorous implant.
Claim 30
Dependent Claim
19 words
The MOSFET of claim 21 , wherein each of the third and fourth implanted regions comprise a boron implant.
Claim 31
Dependent Claim
16 words
The MOSFET of claim 21 , wherein the graded junctions comprise a low dosage phosphorous implant.
References Cited (Backward Citations)
US4939386A
Cited
US5021851A
Cited
US4949136A
Cited
US5218221A
Cited
US5217910A
Cited
JPH0613401A
Cited
JPH06132489A
Cited
WO1994019830A1
Cited
US5716862A
Cited
US5376566A
Cited
US5770505A
Cited
US5726479A
Cited
US5719424A
Cited
US6046472A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-12-16 | 2006-06-17 | 2006-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-16 | 2010-06-17 | 2010-12-17 | $3760.00 | Window Closed / Lapsed |
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