US6480406B1
Expired / Lapsed
US
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Content addressable memory cell
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2001-08-22
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Granted: 2002-11-12
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Expires: 2021-08-22
Abstract
Abstract Architecture, circuitry, and methods are provided for producing a content addressable memory (CAM). The CAM includes one or more CAM cells arranged in an array. Each CAM cell is symmetrical about its x- and y-axis to form rows and columns of the array. Additionally, each CAM cell can use either SRAM or DRAM storage cells implemented in either a binary or ternary arrangement. If the CAM cell is a ternary SRAM design, then the cell size is no more than 4 microns by 1-½ microns, assuming a 0.15 micron critical dimension. Critical dimension is noted as the smallest resolvable size for the particular process being employed. The CAM cell utilizes a selection circuitry that will disable the compare circuit during times when a compare operation is not being performed. This will ensure the compare circuit will not consume power during, for example, a read or write operation. Each CAM cell uses no more than eight conductors per cell, wherein the conductors are of minimum width and pitch arranged co-planar on a single metal layer. Another metal layer utilizes local interconnects and a pair of conductors which carry the differential bit lines and compare lines. The local interconnects do not extend across the entire cell and, therefore, are localized to only a small region of a cell to effectuate power and ground supplies to the CAM cell.
Inventors
- 👤 Bo Jin
- 👤 Manoj Roge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:53
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
37 words
A content addressable memory cell, comprising: a compare circuit; and a multiplexer adapted to selectively couple power to the compare circuit in lieu of ground during times when the memory cell services a read or write operation.
Claim 2
Dependent Claim
37 words
A content addressable memory cell, comprising: a compare circuit; and a multiplexer adapted to selectively couple power to the compare circuit in lieu of ground during times when the memory cell services a read or write operation.
Claim 3
Dependent Claim
18 words
The memory cell as recited in claim 1 , wherein the compare circuit comprises an exclusive NOR circuit.
Claim 4
Dependent Claim
86 words
The memory cell as recited in claim 2 , wherein the exclusive NOR circuit comprises: a match line coupled to receive a signal that indicates the contents within the memory cell matches data forwarded to the memory cell; first and second pairs of transistors, wherein each pair is coupled between the match line and a common node, and wherein the common node is coupled to receive power from the multiplexer in lieu of ground during times when the memory cell services the read or write operation.
Claim 5
Dependent Claim
52 words
The memory cell as recited in claim 1 , wherein the multiplexer includes a pair of input conductors upon which a power supply and a ground supply are connected, and wherein the multiplexer further includes an enable conductor upon which signals that instruct the memory to read or write data are connected.
Claim 6
Dependent Claim
33 words
The memory cell as recited in claim 4 , wherein the signals are produced by a controller during times when the memory cell is called upon to service the read or write operation.
Claim 7
Dependent Claim
35 words
A content addressable memory cell, comprising: a compare circuit; and a multiplexer adapted to selectively couple ground to the compare circuit in lieu of power during times when the memory cell services a compare operation.
Claim 8
Dependent Claim
35 words
A content addressable memory cell, comprising: a compare circuit; and a multiplexer adapted to selectively couple ground to the compare circuit in lieu of power during times when the memory cell services a compare operation.
Claim 9
Dependent Claim
18 words
The memory cell as recited in claim 6 , wherein the compare circuit comprises an exclusive NOR circuit.
Claim 10
Dependent Claim
84 words
The memory cell as recited in claim 7 , wherein the exclusive NOR circuit comprises: a match line coupled to receive a signal that indicates the contents within the memory cell matches data forwarded to the memory cell; first and second pairs of transistors, wherein each pair is coupled between the match line and a common node, and wherein the common node is coupled to receive ground from the multiplexer in lieu of power during times when the memory cell services the compare operation.
Claim 11
Dependent Claim
51 words
The memory cell as recited in claim 6 , wherein the multiplexer includes a pair of input conductors upon which a power supply and a ground supply are connected, and wherein the multiplexer further includes an enable conductor upon which a signal that instruct the memory to compare data is connected.
Claim 12
Dependent Claim
42 words
The memory cell as recited in claim 9 , wherein the signal is produced by a controller during times when the memory cell is called upon to compare data forwarded to the memory cell with data previously stored in the memory cell.
Claim 13
Dependent Claim
40 words
The memory cell as recited in claim 6 , wherein the multiplexer is further adapted to couple ground to the compare circuit in lieu of power during times when the memory cell is called upon to service the compare operation.
Claim 14
Independent Claim
64 words
A method for minimizing power consumption within a content addressable memory cell, comprising: applying power to a compare circuit within the memory cell during a first time in which the memory cell is undergoing a read or write operation; and applying ground to the compare circuit within the memory cell during a second time in which the memory cell is undergoing a compare operation.
Claim 15
Independent Claim
64 words
A method for minimizing power consumption within a content addressable memory cell, comprising: applying power to a compare circuit within the memory cell during a first time in which the memory cell is undergoing a read or write operation; and applying ground to the compare circuit within the memory cell during a second time in which the memory cell is undergoing a compare operation.
Claim 16
Dependent Claim
48 words
The method as recited in claim 12 , wherein applying power during the first time comprises detecting a signal which initiates the read or write operation and forwarding the signal to a multiplexer for placing a power supply signal forwarded to the multiplexer input upon the compare circuit.
Claim 17
Dependent Claim
46 words
The method as recited in claim 12 , wherein applying ground during the second time comprises detecting a signal which initiates the compare operation and forwarding the signal to a multiplexer for placing a ground supply signal forwarded to the multiplexer input upon the compare circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-11 | 2006-05-13 | 2006-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-11 | 2010-05-13 | 2010-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-11 | 2014-05-13 | 2014-11-12 | $7700.00 | Window Closed / Lapsed |