US5802567A
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Mechanism for managing offset and aliasing conditions within a content-addressable memory-based cache memory
Assignee: International Business Machines Corp
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Filing: 1996-10-31
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Granted: 1998-09-01
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Expires: 2016-10-31
Abstract
Abstract A cache memory having a mechanism for managing offset and aliasing conditions is disclosed. In accordance with a preferred embodiment of the invention, the cache memory comprises a first directory circuit, a second directory circuit, a multiple number of most recently used bits, and a multiple number of set/reset circuits. The first directory circuit, having multiple caches lines, is utilized to receive partial effective addresses. The second directory circuit is utilized to receive an output from the first directory circuit. A most recently used bit is associated with each cache line within the first directory circuit. The set/reset circuit, coupled to each of the most recently used bits, is utilized to set one of the most recently used bits to a first state while concurrently resetting the rest of the most recently used bits to a second state within a single cycle during an occurrence of an offset or aliasing conditions such that offset or aliasing conditions can be more efficiently managed.
Inventors
- 👤 Peichun Peter Liu
- 👤 Rajinder Paul Singh
- 👤 Shih-Hsiung Steve Tung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/126; G06F12/127; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054; G06F12/0802; G06F12/0864
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
158 words
A cache memory having a mechanism for managing offset and aliasing conditions, said cache memory comprising: a first directory circuit for receiving partial effective addresses, wherein said first directory circuit includes a plurality of cache lines; a second directory circuit for receiving an output from said first directory circuit; a plurality of most recently used bits, wherein each of said plurality of most recently used bits is associated with a respective one of said plurality of cache lines ; and a set/reset circuit coupled to each of said plurality of most recently used bits, wherein said set/reset circuit includes a means for setting one of said plurality of most recently used bits to a first state while concurrently resetting the rest of said plurality of most recently used bits to a second state within a single clock cycle during an occurrence of an offset or aliasing condition, such that offset and aliasing conditions can be more efficiently managed.
Claim 2
Dependent Claim
158 words
A cache memory having a mechanism for managing offset and aliasing conditions, said cache memory comprising: a first directory circuit for receiving partial effective addresses, wherein said first directory circuit includes a plurality of cache lines; a second directory circuit for receiving an output from said first directory circuit; a plurality of most recently used bits, wherein each of said plurality of most recently used bits is associated with a respective one of said plurality of cache lines ; and a set/reset circuit coupled to each of said plurality of most recently used bits, wherein said set/reset circuit includes a means for setting one of said plurality of most recently used bits to a first state while concurrently resetting the rest of said plurality of most recently used bits to a second state within a single clock cycle during an occurrence of an offset or aliasing condition, such that offset and aliasing conditions can be more efficiently managed.
Claim 3
Dependent Claim
86 words
The cache memory having a mechanism for managing offset and aliasing conditions according to claim 1, wherein said means for setting and resetting operates according to a truth table as follows: ______________________________________
WORDLINE ENABLE EMATCH
signal signal signal MRU bit
______________________________________
0 0 1 as is
1 0 don't care
1
0 0 0 0
______________________________________ wherein said WORDLINE signal, said ENABLE signal, and said EMATCH signal are inputs, wherein said EMATCH signal indicates whether or not there is a match within said first directory circuit.
Claim 4
Dependent Claim
26 words
The cache memory having a mechanism for managing offset and aliasing conditions according to claim 1, wherein said first and second directory circuits are content-addressable memories.
Claim 5
Dependent Claim
32 words
The cache memory having a mechanism for managing offset and aliasing conditions according to claim 1, wherein said first state is a logical "1" and said second state is a logical "0."
Claim 6
Dependent Claim
31 words
The cache memory having a mechanism for managing offset and aliasing conditions according to claim 1, wherein each of said plurality of most recently used bits is a static memory cell.
Claim 7
Independent Claim
115 words
A method for managing offset and aliasing conditions in a cache memory, wherein said cache memory includes a first directory circuit and a secondary directory circuit, wherein said first directory circuit includes a plurality of cache lines, said method comprising the steps of: associating a most recent used bit to each of said plurality of cache lines within said first directory circuit; setting one of said plurality of most recently used bits to a first state while concurrently resetting the rest of said plurality of most recently used bits to a second state within a single cycle during an occurrence of an offset or aliasing condition such that offset and aliasing conditions can be managed.
Claim 8
Independent Claim
115 words
A method for managing offset and aliasing conditions in a cache memory, wherein said cache memory includes a first directory circuit and a secondary directory circuit, wherein said first directory circuit includes a plurality of cache lines, said method comprising the steps of: associating a most recent used bit to each of said plurality of cache lines within said first directory circuit; setting one of said plurality of most recently used bits to a first state while concurrently resetting the rest of said plurality of most recently used bits to a second state within a single cycle during an occurrence of an offset or aliasing condition such that offset and aliasing conditions can be managed.
Claim 9
Dependent Claim
87 words
The method for managing offset an d aliasing conditions in a cache memory according to claim 6, wherein said step of setting and resetting operates according to a truth table as follows: ______________________________________
WORDLINE ENABLE EMATCH
signal signal signal MRU bit
______________________________________
0 0 1 as is
1 0 don't care
1
0 0 0 0
______________________________________ wherein said WORDLINE signal, said ENABLE signal, and said EMATCH signal are inputs, wherein said EMATCH signal indicates whether or not there is a match within said first directory circuit.
Claim 10
Dependent Claim
168 words
A data processing system comprising: a processor; a main memory; a cache memory for temporarily storing blocks of information from said main memory, said cache memory includes: a first directory circuit for receiving partial effective addresses, wherein said first directory circuit includes a plurality of cache lines; a second directory circuit for receiving an output from said first directory circuit; a plurality of most recently used bits, wherein each of said plurality of most recently used bits is associated with a respective one of said plurality of cache lines; and a set/reset circuit coupled to each of said plurality of most recently used bits, wherein said set/reset circuit includes a means for setting one of said plurality of most recently used bits to a first state while concurrently resetting the rest of said plurality of most recently used bits to a second state within a single clock cycle during an occurrence of an offset or aliasing condition, such that offset and aliasing conditions can be more efficiently managed.
Claim 11
Dependent Claim
168 words
A data processing system comprising: a processor; a main memory; a cache memory for temporarily storing blocks of information from said main memory, said cache memory includes: a first directory circuit for receiving partial effective addresses, wherein said first directory circuit includes a plurality of cache lines; a second directory circuit for receiving an output from said first directory circuit; a plurality of most recently used bits, wherein each of said plurality of most recently used bits is associated with a respective one of said plurality of cache lines; and a set/reset circuit coupled to each of said plurality of most recently used bits, wherein said set/reset circuit includes a means for setting one of said plurality of most recently used bits to a first state while concurrently resetting the rest of said plurality of most recently used bits to a second state within a single clock cycle during an occurrence of an offset or aliasing condition, such that offset and aliasing conditions can be more efficiently managed.
Claim 12
Dependent Claim
78 words
The data processing system according to claim 8, wherein said means for setting and resetting operates according to a truth table as follows: ______________________________________
WORDLINE ENABLE EMATCH
signal signal signal MRU bit
______________________________________
0 0 1 as is
1 0 don't care
1
0 0 0 0
______________________________________ wherein said WORDLINE signal, said ENABLE signal, and said EMATCH signal are inputs, wherein said EMATCH signal indicates whether or not there is a match within said first directory circuit.
Claim 13
Dependent Claim
18 words
The data processing system according to claim 8, wherein said first and second directory circuits are content-addressable memories.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |