US6470408B1
Expired / Lapsed
US
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Apparatus and method for delivering interrupts via an APIC bus to IA-32 processors
Assignee: Hewlett Packard Development Co LP
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Filing: 1999-04-14
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Granted: 2002-10-22
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Expires: 2019-04-14
Abstract
Abstract An apparatus and a method are provided to distribute interrupts from a system bus to Intel® Architecture (IA)-32 applications processors. The apparatus includes a bridge that couples a processor bus to the system bus. In addition, the bridge is coupled to an advanced programmable interrupt controller (APIC) by an APIC bus. The bridge monitors the system bus for interrupts and converts selected interrupt transactions into APIC messages. The bridge then sends the APIC messages to the APIC bus. Each of the applications processors is also coupled to one of many APIC buses. The applications processor that is the target of the interrupt transaction receives the APIC message and executes an interrupt handler routine. The apparatus and method also incorporate interrupt transaction buffering and throttling.
Inventors
- 👤 John A. Morrison
- 👤 Robert J. Blakely
- 👤 Leo J. Embry
- 👤 Michael S. Allison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:04
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
101 words
An apparatus for distributing interrupts in a multi-processor architecture computer system, comprising: a system bus that provides interrupts; a bridge coupled to the system bus; and a plurality of applications processors coupled to the bridge, wherein the system bus supplies the interrupts as interrupt transactions and wherein the bridge reads an interrupt transaction to determine a target applications processor, converts the interrupt transaction into an interrupt message, and supplies the interrupt message to the target applications processor, wherein the interrupt transaction includes an applications processor identification and wherein the bridge identifies the target applications processor by reading the applications processor identification.
Claim 2
Independent Claim
101 words
An apparatus for distributing interrupts in a multi-processor architecture computer system, comprising: a system bus that provides interrupts; a bridge coupled to the system bus; and a plurality of applications processors coupled to the bridge, wherein the system bus supplies the interrupts as interrupt transactions and wherein the bridge reads an interrupt transaction to determine a target applications processor, converts the interrupt transaction into an interrupt message, and supplies the interrupt message to the target applications processor, wherein the interrupt transaction includes an applications processor identification and wherein the bridge identifies the target applications processor by reading the applications processor identification.
Claim 3
Dependent Claim
46 words
The apparatus of claim 1 , further comprising: a processor bus coupled to the bridge and the plurality of applications processors; and an advanced programmable interrupt (APIC) bus coupled to the plurality of applications processors, wherein the bridge supplies the interrupt message to the APIC bus.
Claim 4
Dependent Claim
17 words
The apparatus of claim 1 , wherein the bridge formats the interrupt message as an APIC message.
Claim 5
Dependent Claim
45 words
The apparatus of claim 1 , wherein the bridge, comprises: a buffer that stores the interrupt transactions for delivery to an applications processor; a throttling mechanism that prevents the system bus from suppling interrupt transactions for a given applications processor when the buffer is full.
Claim 6
Dependent Claim
18 words
The apparatus of claim 1 , wherein the bridge converts the interrupt transaction into an appropriate APIC message.
Claim 7
Dependent Claim
40 words
The apparatus of claim 5 , wherein when the bridge provides the APIC message for the external interrupt, the target applications processor returns an interrupt acknowledge to the bridge and the bridge returns the interrupt acknowledge to the system bus.
Claim 8
Dependent Claim
30 words
The apparatus of claim 1 , wherein the interrupt transaction includes an applications processor identification and wherein the bridge identifies the target applications processor by reading the applications processor identification.
Claim 9
Dependent Claim
23 words
The apparatus of claim 1 , wherein the system bus is coupled to an IA-64 component and the applications processors are IA-32 components.
Claim 10
Independent Claim
112 words
A method for distributing interrupts in a computer system, comprising: receiving an interrupt transaction indicating a pending interrupt at a system bus; reading the interrupt transaction by a plurality of bridges to determine a target applications processor from a plurality of applications processors, wherein the reading step comprises identifying the target applications processor by reading an identification of the target applications processor included in the interrupt transaction; transferring the interrupt transaction to a bridge, wherein the bridge is coupled to one or more applications processors by a processor bus; converting the transferred interrupt transaction into an interrupt message; and sending the interrupt message to the target applications processor over an APIC bus.
Claim 11
Independent Claim
112 words
A method for distributing interrupts in a computer system, comprising: receiving an interrupt transaction indicating a pending interrupt at a system bus; reading the interrupt transaction by a plurality of bridges to determine a target applications processor from a plurality of applications processors, wherein the reading step comprises identifying the target applications processor by reading an identification of the target applications processor included in the interrupt transaction; transferring the interrupt transaction to a bridge, wherein the bridge is coupled to one or more applications processors by a processor bus; converting the transferred interrupt transaction into an interrupt message; and sending the interrupt message to the target applications processor over an APIC bus.
Claim 12
Dependent Claim
30 words
The method of claim 9 , wherein the reading step, comprises: identifying the target applications processor by reading an identification of the target applications processor included in the interrupt transaction.
Claim 13
Dependent Claim
14 words
The method of claim 9 , wherein the interrupt message is an APIC message.
Claim 14
Dependent Claim
66 words
The method of claim 9 , wherein the interrupt transaction corresponds to an external interrupt, the method further comprising: returning an interrupt acknowledge from the target applications processor to the processor bus in response to the interrupt message; providing the returned interrupt acknowledge from the bridge to the system bus; and providing the interrupt vector in response to the returned interrupt acknowledge on the system bus.
Claim 15
Dependent Claim
44 words
The method of claim 9 , wherein the target applications processor is targeted by more than one interrupt, further comprising: buffering a subsequent interrupt transaction in a buffer until completion of delivering a prior interrupt in the target applications processor on the APIC bus.
Claim 16
Dependent Claim
33 words
The method of claim 13 , wherein the target applications processor is targeted by more than one interrupt, further comprising: throttling the system bus when a capacity of the buffer will be exceeded.
Claim 17
Dependent Claim
22 words
The method of claim 9 , wherein the applications processors are IA-32 processors and wherein the computer system comprises IA-64 architecture components.
Claim 18
Independent Claim
118 words
A system for distributing interrupts, comprising: a system bus; an input/output (I/O) controller coupled to the system bus, wherein the I/O controller receives interrupts from devices and issues the interrupts on the system bus; a bridge coupled to the system bus; a processor bus coupled to the bridge; applications processors coupled to the processor bus; and and advanced programmable interrupt controller (APIC) bus coupled to the applications processor and the bridge, wherein the bridge converts interrupt transactions into APIC messages and provides the APIC messages on the APIC bus, and wherein the bridge determines a target applications processor to receive an APIC message by reading an applications processor identification and a node identification included in an interrupt transaction.
Claim 19
Independent Claim
118 words
A system for distributing interrupts, comprising: a system bus; an input/output (I/O) controller coupled to the system bus, wherein the I/O controller receives interrupts from devices and issues the interrupts on the system bus; a bridge coupled to the system bus; a processor bus coupled to the bridge; applications processors coupled to the processor bus; and and advanced programmable interrupt controller (APIC) bus coupled to the applications processor and the bridge, wherein the bridge converts interrupt transactions into APIC messages and provides the APIC messages on the APIC bus, and wherein the bridge determines a target applications processor to receive an APIC message by reading an applications processor identification and a node identification included in an interrupt transaction.
Claim 20
Dependent Claim
28 words
The system of claim 16 , wherein the bridge comprises: a buffer that stores pending interrupt transactions; and a throttle that limits interrupt transactions on the system bus.
Claim 21
Dependent Claim
24 words
The system of claim 16 , wherein the bridge converts interrupt transactions into APIC messages and provides the APIC messages on the APIC bus.
Claim 22
Dependent Claim
34 words
The system of claim 18 , wherein the bridge determines a target applications processor to receive an APIC message by reading an applications processor identification and a node identification included in the interrupt transaction.
Claim 23
Dependent Claim
21 words
The system of claim 16 , wherein the applications processors are IA-32 processors and wherein the system comprises IA-64 architecture components.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-21 | 2006-04-22 | 2006-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-21 | 2010-04-22 | 2010-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-21 | 2014-04-22 | 2014-10-22 | $7700.00 | Window Closed / Lapsed |