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US6469555B1
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Apparatus and method for generating multiple clock signals from a single loop circuit
Assignee: Rambus Inc
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Filing: 2000-08-18
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Granted: 2002-10-22
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Expires: 2020-08-18
Abstract
Abstract A delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period. A second delay element is coupled to receive the first clock signal from the delay-locked loop circuit. The second delay element also outputs a second clock signal that is delayed relative to the first clock signal by the first time period. The delay-locked loop circuit may include a phase detector to identify phase differences between the first clock signal and the reference clock signal. A third delay element may be coupled between the delay-locked loop circuit and the second delay element.
Inventors
- 👤 Benedict C. Lau
- 👤 Stefanos Sidiropoulos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:44
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
102 words
An apparatus comprising: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period; and a third delay element coupled between the delay-locked loop circuit and the second delay element.
Claim 2
Independent Claim
102 words
An apparatus comprising: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period; and a third delay element coupled between the delay-locked loop circuit and the second delay element.
Claim 3
Dependent Claim
16 words
An apparatus as recited in claim 1 wherein the third delay element is a clock buffer.
Claim 4
Dependent Claim
18 words
An apparatus as recited in claim 1 wherein the third delay element is coupled to an output driver.
Claim 5
Dependent Claim
31 words
An apparatus as recited in claim 1 wherein the delay-locked loop circuit further includes a phase detector to identify phase differences between the first clock signal and the reference clock signal.
Claim 6
Dependent Claim
16 words
An apparatus as recited in claim 4 wherein the phase detector is a zero phase detector.
Claim 7
Dependent Claim
28 words
An apparatus as recited in claim 1 wherein the delay-locked loop circuit further includes a 180 degree phase shifter to adjust the phase of the first clock signal.
Claim 8
Dependent Claim
128 words
A memory system comprising: a memory storage device; a data bus coupled to the memory storage device; and a memory controller coupled to the data bus, the memory controller including: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period; and a third delay element coupled between the delay-locked loop circuit and second delay element.
Claim 9
Dependent Claim
128 words
A memory system comprising: a memory storage device; a data bus coupled to the memory storage device; and a memory controller coupled to the data bus, the memory controller including: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period; and a third delay element coupled between the delay-locked loop circuit and second delay element.
References Cited (Backward Citations)
US6229363B1
Cited
US6140854A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-21 | 2006-04-22 | 2006-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-21 | 2010-04-22 | 2010-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-21 | 2014-04-22 | 2014-10-22 | $7700.00 | Window Closed / Lapsed |