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US6460010B1
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Method and apparatus for statistical compilation
Assignee: Nokia Canada Inc
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Filing: 1999-09-22
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Granted: 2002-10-01
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Expires: 2019-09-22
Abstract
Abstract A method and apparatus for statistical compilation is presented. The statistical compilation circuit includes a multi-bank memory that stores a plurality of statistics, where a statistic component portion for each statistic is stored in each of the plurality of banks in the multi-bank memory. An arbitration block is operably coupled to receive at least one statistical update stream. Each statistical update stream includes a plurality of statistical updates, where each statistical update includes a statistic identifier and an update operand. The arbitration block schedules received statistical updates to produce a scheduled update stream. A control block operably coupled to the arbitration block and the multi-bank memory executes the updates included in the scheduled update stream. The control block retrieves the current value of one of the statistic component portions from one of the memory banks and combines the current value with the update operand of a corresponding statistical update. The resulting updated component value is then stored back into the memory bank from which it was read. When a processing block that is operably coupled to the control block issues a statistic request corresponding to a particular requested statistic, the control block fetches each of the component portions from each of the memory banks corresponding to that particular statistic and combines the component portions to produce a total statistic value.
Inventors
- 👤 Gordon G. G. Hanes
- 👤 Mainz Tong
- 👤 Martin Darwin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:59
CPC Classifications
H; H04; H04L; H04L41/00; H04L41/24
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
310 words
A statistical compilation circuits comprising: a multi-bank memory, wherein the multi-bank memory stores a plurality of statistics, wherein a statistic component portion for each statistic is stored in each of a plurality of banks of the multi-bank memory; an arbitration block operably coupled to receive at least one statistical update stream, wherein the at least one statistical update stream includes a plurality of statistical updates, wherein a statistical update includes a statistic identifier and an update operand, wherein the arbitration block schedules received statistical updates to produce a scheduled update stream; a control block operably coupled to the arbitration block and the multi-bank memory, wherein the control block compiles a set of read operations based on a portion of the scheduled update stream, wherein each read operation corresponds to a scheduled update in the portion of the scheduled update stream, wherein a read operation for a particular scheduled update retrieves a component value of one of the statistic component portions from one of the plurality of banks of the multi-bank memory for a statistic corresponding to the particular scheduled update, wherein the control block combines the operand for the particular scheduled update with the component value to produce an updated component value, wherein the control block compiles a set of write operations corresponding to the set of read operations, wherein the set of write operations overwrite component values fetched by the set of read operations with corresponding updated component values produced through combination operations; and a processing block operably coupled to the control block, wherein the processing block issues statistic requests corresponding to a requested statistic to the control block, wherein the control block retrieves component values for each component portion of the requested statistic from the multi-bank memory, wherein the control block combines the component values that are retrieved to produce a total statistic value for the requested statistic.
Claim 2
Dependent Claim
310 words
A statistical compilation circuits comprising: a multi-bank memory, wherein the multi-bank memory stores a plurality of statistics, wherein a statistic component portion for each statistic is stored in each of a plurality of banks of the multi-bank memory; an arbitration block operably coupled to receive at least one statistical update stream, wherein the at least one statistical update stream includes a plurality of statistical updates, wherein a statistical update includes a statistic identifier and an update operand, wherein the arbitration block schedules received statistical updates to produce a scheduled update stream; a control block operably coupled to the arbitration block and the multi-bank memory, wherein the control block compiles a set of read operations based on a portion of the scheduled update stream, wherein each read operation corresponds to a scheduled update in the portion of the scheduled update stream, wherein a read operation for a particular scheduled update retrieves a component value of one of the statistic component portions from one of the plurality of banks of the multi-bank memory for a statistic corresponding to the particular scheduled update, wherein the control block combines the operand for the particular scheduled update with the component value to produce an updated component value, wherein the control block compiles a set of write operations corresponding to the set of read operations, wherein the set of write operations overwrite component values fetched by the set of read operations with corresponding updated component values produced through combination operations; and a processing block operably coupled to the control block, wherein the processing block issues statistic requests corresponding to a requested statistic to the control block, wherein the control block retrieves component values for each component portion of the requested statistic from the multi-bank memory, wherein the control block combines the component values that are retrieved to produce a total statistic value for the requested statistic.
Claim 3
Dependent Claim
16 words
The circuit of claim 1 , wherein the multi-bank memory is a single SDRAM integrated circuit.
Claim 4
Dependent Claim
16 words
The circuit of claim 1 , wherein the multi-bank memory is plurality of memory integrated circuits.
Claim 5
Dependent Claim
49 words
The circuit of claim 1 , wherein the multi-bank memory further comprises a plurality of multi-bank memories, wherein each multi-bank memory is used for alternating time intervals such that statistics from at least a most recent time interval are maintained while a current set of statistics is being compiled.
Claim 6
Dependent Claim
51 words
The circuit of claim 4 further comprises a plurality of memory controllers, wherein each memory controller is operably coupled to the control block and to a corresponding one of the plurality of multi-bank memories, wherein the plurality of memory controllers allow concurrent multiple memory operations to the plurality of multi-bank memories.
Claim 7
Dependent Claim
31 words
The circuit of claim 1 , wherein the arbitration block further comprises a receipt sequenced priority encoder such that statistical updates are performed in temporal order based on order of receipt.
Claim 8
Dependent Claim
53 words
The circuit of claim 6 , wherein the receipt sequenced priority encoder further comprises a first in first serviced buffer that stores a set of bits for each statistical update receipt interval, wherein the set of bits indicates from which statistical update stream statistical updates were received for the statistical update receipt interval.
Claim 9
Dependent Claim
52 words
The circuit of claim 1 , wherein the arbitration block schedules received statistical updates based on a weighted fair queuing technique, wherein the weighted fair queuing technique schedules received statistical updates based on at least one of: priority level of each statistical update stream, and loading level of each statistical update stream.
Claim 10
Dependent Claim
28 words
The circuit of claim 1 further comprises at least one stream buffer operably coupled to the arbitration block, wherein each stream buffer buffers a corresponding statistical update stream.
Claim 11
Dependent Claim
33 words
The circuit of claim 1 further comprises an scheduled update stream buffer operably coupled to the arbitration block and the control block, wherein the scheduled update stream buffer buffers the scheduled update stream.
Claim 12
Dependent Claim
32 words
The circuit of claim 1 further comprises statistic request buffer operably coupled to the control block and the processing block, wherein the statistic request buffer buffers statistic requests from the processing block.
Claim 13
Dependent Claim
55 words
The circuit of claim 1 further comprises an overflow block operably coupled to the control block, wherein the overflow block stores indications of overflow conditions that result when an updated component value overflows an allocated bit width, wherein overflow conditions are included when the control block combines component values in response to a statistic request.
Claim 14
Dependent Claim
58 words
The circuit of claim 1 , wherein the control block further comprises an update combination block, wherein the update combination block detects multiple updates to a single statistic and combines the operands of the multiple updates to produce a combined operand that is combined with the component value to produce the updated component value for the single statistic.
Claim 15
Dependent Claim
16 words
The circuit of claim 13 , wherein the update combination block includes a content addressable memory.
Claim 16
Dependent Claim
25 words
The circuit of claim 1 , wherein the control block controls servicing of statistic requests and statistical updates based on a control block arbitration scheme.
Claim 17
Dependent Claim
33 words
The circuit of claim 1 , wherein the control block further comprises an adder that combines the operand for the particular schedule update with the component value to produce the updated component value.
Claim 18
Dependent Claim
23 words
The circuit of claim 1 , wherein each statistical update is a single command issued by a datapath processor in a communications system.
Claim 19
Dependent Claim
28 words
The circuit of claim 17 , wherein the plurality of statistics include statistics corresponding to at least one of: packet traffic and cell traffic in the communications system.
Claim 20
Dependent Claim
42 words
The circuit of claim 18 , wherein the plurality of statistics include statistics corresponding to at least one of: network performance statistics, billing statistics, class of service traffic statistics, discard statistics, and statistics concerning traffic flow along particular paths in the network.
Claim 21
Dependent Claim
20 words
The circuit of claim 1 , wherein the arbitration block schedules received statistical updates based on a round-robin scheduling scheme.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-30 | 2006-04-01 | 2006-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-30 | 2010-04-01 | 2010-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-30 | 2014-04-01 | 2014-10-01 | $7700.00 | Window Closed / Lapsed |