Patent US6457095B1 successfully refreshed from Google Patents.
US6457095B1
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Method and apparatus for synchronizing dynamic random access memory exiting from a low power state
Assignee: Intel Corp
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Filing: 1999-12-13
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Granted: 2002-09-24
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Expires: 2019-12-13
Abstract
Abstract A method and apparatus for exiting a dynamic random access memory from a low power state is provided. The exit from the low power state is first initiated. After the expiration of an exit delay period, a quiet time command is routed through a queue circuit. In one embodiment the use of a bypass circuit allows the interruption of the memory pipeline with a subsequent restart of the pipeline without excessive delay. A flexible clock is delayed by the onset of the quiet time command until the subsequent quiet time event.
Inventors
- 👤 Andrew M. Volk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:56
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039; G11C5/00; G11C5/14; G11C5/147; G11C7/20
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
64 words
A method comprising: initiating an exit from a low power state; waiting during an exit delay time period; scheduling a quiet time command in an addressing pipeline, where a memory transitions from the low power state to a normal power state in response to a quiet time in response to the quiet time command; and delaying a clock signal to ensure proper exiting timing.
Claim 2
Independent Claim
64 words
A method comprising: initiating an exit from a low power state; waiting during an exit delay time period; scheduling a quiet time command in an addressing pipeline, where a memory transitions from the low power state to a normal power state in response to a quiet time in response to the quiet time command; and delaying a clock signal to ensure proper exiting timing.
Claim 3
Dependent Claim
26 words
The method of claim 1 , wherein said delaying a clock signal includes delaying said clock signal until a quiet time follows the quiet time command.
Claim 4
Dependent Claim
20 words
The method of claim 2 , wherein delaying the clock signal includes delaying a clock edge of the clock signal.
Claim 5
Dependent Claim
15 words
The method of claim 3 , wherein delaying the clock signal utilizes a state machine.
Claim 6
Dependent Claim
30 words
The method of claim 2 , wherein delaying the clock signal includes delaying a clock edge of the clock signal and resynchronizing the clock signal with a free running clock.
Claim 7
Dependent Claim
18 words
The method of claim 5 , wherein resynchronizing the clock signal utilizes a counter and a synchronous multiplexor.
Claim 8
Dependent Claim
14 words
The method of claim 2 , wherein said scheduling includes bypassing said addressing pipeline.
Claim 9
Independent Claim
31 words
A method comprising: issuing a quiet time command; waiting during an exit delay time period; and synchronizing a clock signal to a quiet time occurring subsequent to the quiet time command.
Claim 10
Independent Claim
31 words
A method comprising: issuing a quiet time command; waiting during an exit delay time period; and synchronizing a clock signal to a quiet time occurring subsequent to the quiet time command.
Claim 11
Dependent Claim
27 words
The method of claim 8 wherein said step of synchronizing includes delaying a clock signal transition of said clock signal until the occurrence of said quiet time.
Claim 12
Dependent Claim
22 words
The method of claim 9 wherein said step of delaying said clock signal transition occurs subsequent to the exit delay time period.
Claim 13
Dependent Claim
25 words
The method of claim 9 wherein said step of delaying said clock signal transition includes monitoring access-control signals for the presence of said quiet time.
Claim 14
Dependent Claim
25 words
The method of claim 8 wherein said step of synchronizing includes extending said quiet time until a clock signal transition of said clock signal occurs.
Claim 15
Dependent Claim
18 words
The method of claim 12 wherein said step of extending said quiet time includes stalling a pipeline queue.
Claim 16
Dependent Claim
18 words
The method of claim 13 wherein said step of stalling a pipeline queue includes delaying a load signal.
Claim 17
Independent Claim
72 words
An apparatus comprising: means for initiating an exit from a low power state; means for waiting during a exit delay time period; means for scheduling a quiet time command in an addressing pipeline, where a memory transitions from the low power state to a normal power state in response to a quiet time in response to the quiet time command; and means for delaying a clock signal to ensure proper exiting timing.
Claim 18
Independent Claim
72 words
An apparatus comprising: means for initiating an exit from a low power state; means for waiting during a exit delay time period; means for scheduling a quiet time command in an addressing pipeline, where a memory transitions from the low power state to a normal power state in response to a quiet time in response to the quiet time command; and means for delaying a clock signal to ensure proper exiting timing.
Claim 19
Dependent Claim
92 words
A circuit comprising: a scheduler configured to control a command pipeline and initiate an exit from a low power state; the scheduler further configured to control an exit delay time period; a queue circuit coupled to the scheduler configured to insert a quiet time command into an address pipeline, where a memory transitions from the low power state to a normal power state in response to a quiet time in response to the quiet time command; and a circuit element configured to delay a first clock signal to ensure proper exiting timing.
Claim 20
Dependent Claim
92 words
A circuit comprising: a scheduler configured to control a command pipeline and initiate an exit from a low power state; the scheduler further configured to control an exit delay time period; a queue circuit coupled to the scheduler configured to insert a quiet time command into an address pipeline, where a memory transitions from the low power state to a normal power state in response to a quiet time in response to the quiet time command; and a circuit element configured to delay a first clock signal to ensure proper exiting timing.
Claim 21
Dependent Claim
26 words
The circuit of claim 16 , wherein said circuit element includes a clock circuit coupled to the queue circuit configured to delay said first clock signal.
Claim 22
Dependent Claim
24 words
The circuit of claim 17 , wherein the clock circuit delays the first clock signal until a quiet time follows the quiet me command.
Claim 23
Dependent Claim
27 words
The circuit of claim 18 , wherein the clock circuit delays a clock edge of the first clock signal and then initiates a free running clock signal.
Claim 24
Dependent Claim
32 words
The circuit of claim 18 , wherein the clock circuit delays a clock edge of the first clock signal and then resynchronizes the first clock signal with a free running clock signal.
Claim 25
Dependent Claim
23 words
The circuit of claim 20 , wherein the clock circuit includes a free running counter configured to generate the free running clock signal.
Claim 26
Dependent Claim
17 words
The circuit of claim 21 , wherein the free running counter is coupled to a synchronous multiplexor.
Claim 27
Dependent Claim
22 words
The circuit of claim 16 , further comprising a bypass circuit coupled to the queue circuit configured to interrupt the address pipeline.
Claim 28
Dependent Claim
20 words
The circuit of claim 23 , wherein the bypass circuit and the queue circuit are both coupled to a multiplexor.
Claim 29
Dependent Claim
19 words
The circuit of claim 24 , wherein the multiplexor transmits a plurality of access control signals to the memory.
References Cited (Backward Citations)
US5319601A
Cited
US5337285A
Cited
US5781782A
Cited
US5828619A
Cited
JPH1166849A
Cited
US6088290A
Cited
US6112306A
Cited
WO2001043139A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-23 | 2006-03-25 | 2006-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-23 | 2010-03-25 | 2010-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-23 | 2014-03-25 | 2014-09-24 | $7700.00 | Window Closed / Lapsed |