Patent US6457082B1 successfully refreshed from Google Patents.
US6457082B1
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US
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Break event generation during transitions between modes of operation in a computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1999-03-30
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Granted: 2002-09-24
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Expires: 2019-03-30
Abstract
Abstract A break event in a computer system that can operate in one of a plurality of modes, such as a high performance mode and a low power mode is initiated only be logic that that detects when the transition between modes is complete. In the high performance mode, the CPU clock is faster than in the low power mode. The CPU voltage may also be higher in the high performance mode than in the low speed mode. The low power mode may be desirable for a portable computer operating from battery power in order to conserve the battery's charge. The computer system preferably transitions its CPU to a “sleep” state during the mode switch and precludes devices not associated with the mode transition from “waking” the CPU and disturbing the completion of the mode switch. Accordingly, only logic that detects the end of the mode switch can break the CPU out of its sleep state.
Inventors
- 👤 Xinmin Zhang
- 👤 Lan Wang
- 👤 Paul Poh Loh Cheok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:37
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/3296; Y; Y02; Y02D; Y02D10/00; Y02D30/00; Y02D30/50
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
93 words
A computer system, comprising: a CPU module; a bus bridge device coupled to said CPU module; and a peripheral device coupled to said CPU module; wherein said bus bridge device adapted to receive as a general purpose input signal an output signal from said CPU module, the general purpose input signal initiating a break event for transitioning the CPU module out of a sleep state, and the bus bridge device programmed so that only the CPU module output signal can initiate a break event while the CPU module is in the sleep state.
Claim 2
Dependent Claim
93 words
A computer system, comprising: a CPU module; a bus bridge device coupled to said CPU module; and a peripheral device coupled to said CPU module; wherein said bus bridge device adapted to receive as a general purpose input signal an output signal from said CPU module, the general purpose input signal initiating a break event for transitioning the CPU module out of a sleep state, and the bus bridge device programmed so that only the CPU module output signal can initiate a break event while the CPU module is in the sleep state.
Claim 3
Dependent Claim
62 words
The computer system of claim 1 further including stop clock logic coupled to and receiving signals from said CPU module and said bus bridge device, the signal received from the CPU module indicative of an ongoing change in voltage and frequency and the signal received from the bus bridge device asserted by the bus bridge device to stop a CPU clock signal.
Claim 4
Dependent Claim
25 words
The computer system of claim 1 wherein said bus bridge device includes a plurality of programmable registers that are used to configure the break event.
Claim 5
Dependent Claim
13 words
The computer system of claim 1 wherein said peripheral device is a keyboard.
Claim 6
Dependent Claim
14 words
The computer system of claim 1 wherein said peripheral device is an audio system.
Claim 7
Dependent Claim
22 words
The computer system of claim 2 further including a clock generator to generate the CPU clock signal provided to the CPU module.
Claim 8
Dependent Claim
33 words
The computer system of claim 3 wherein the registers include a Device Resource A register in which a bit is set to 0 to disable memory and I/O decoding during the sleep state.
Claim 9
Dependent Claim
32 words
The computer system of claim 3 wherein the registers include a Device Resource E register in which a bit is set to 0 to disable an I/O monitor during the sleep state.
Claim 10
Dependent Claim
32 words
The computer system of claim 3 wherein the registers include a Device Resource F register in which a bit is set to 0 to disable a memory monitor during the sleep state.
Claim 11
Independent Claim
87 words
A method for configuring a break event to transition a computer from a sleep state during a Geyserville mode switch, comprising: (a) detecting a power state change; (b) programming a CPU module to send a Geyserville break event to a bus bridge device in order to transition the CPU from a sleep state; and (c) programming a bus bridge device to initiate the Geyserville break event that can be initiated only upon the bus bridge device detecting the assertion of an input signal by the CPU module.
Claim 12
Independent Claim
87 words
A method for configuring a break event to transition a computer from a sleep state during a Geyserville mode switch, comprising: (a) detecting a power state change; (b) programming a CPU module to send a Geyserville break event to a bus bridge device in order to transition the CPU from a sleep state; and (c) programming a bus bridge device to initiate the Geyserville break event that can be initiated only upon the bus bridge device detecting the assertion of an input signal by the CPU module.
Claim 13
Dependent Claim
26 words
The method of claim 10 wherein step (c) includes: (c1) setting a bit in a register to disable memory and I/O decoding for a device monitor.
Claim 14
Dependent Claim
29 words
The method of claim 10 wherein step (c) includes: (c2) setting a bit in a register to set the polarity for the input signal to initiate the break event.
Claim 15
Dependent Claim
29 words
The method of claim 10 wherein step (c) includes: (c3) setting a bit in a register to enable a trap for a device monitor associated with the break event.
Claim 16
Dependent Claim
30 words
The method of claim 10 wherein step (c) includes: (c4) setting a bit in a register to disable an I/O monitor for a device monitor associated with the break event.
Claim 17
Dependent Claim
30 words
The method of claim 10 wherein step (c) includes: (c4) setting a bit in a register to disable a memory monitor for a device monitor associated with the break event.
Claim 18
Dependent Claim
120 words
A computer system, comprising: a CPU module; a bus bridge device coupled to said CPU module; and stop clock logic coupled to said CPU module and said bus bridge device, said stop clock logic adapted to assert a stop clock control signal that causes a CPU clock signal to stop; wherein said bus bridge device is adapted to receive as a general purpose input signal an output signal from said CPU module, the general purpose input signal initiating a break event for transitioning the CPU module out of a sleep state during a Geyserville mode switch, and the bus bridge device programmed so that only the CPU module output signal can initiate a break event during a Geyserville mode switch.
Claim 19
Dependent Claim
120 words
A computer system, comprising: a CPU module; a bus bridge device coupled to said CPU module; and stop clock logic coupled to said CPU module and said bus bridge device, said stop clock logic adapted to assert a stop clock control signal that causes a CPU clock signal to stop; wherein said bus bridge device is adapted to receive as a general purpose input signal an output signal from said CPU module, the general purpose input signal initiating a break event for transitioning the CPU module out of a sleep state during a Geyserville mode switch, and the bus bridge device programmed so that only the CPU module output signal can initiate a break event during a Geyserville mode switch.
Claim 20
Dependent Claim
46 words
The computer system of claim 16 wherein said stop clock logic includes an AND gate that receives a signal asserted by the bus bridge device to stop the CPU clock signal and receives a signal from the CPU module indicative of an ongoing Geyserville mode switch.
Claim 21
Dependent Claim
31 words
The computer system of claim 16 wherein the bus bridge device asserts an SMI when the general purpose input signal is asserted by the CPU module to initiate a break event.
Claim 22
Dependent Claim
25 words
The computer system of claim 16 wherein the CPU module enables a trap for the general purpose input signal used to initiate the break event.
Claim 23
Dependent Claim
23 words
The computer system of claim 16 wherein the CPU module disables I/O and memory monitoring cycles associated with the general purpose input signal.
Claim 24
Dependent Claim
72 words
The computer system of claim 17 further including a clock generator disposed between said stop clock logic and said CPU module, that generates a periodic signal that is provided to the CPU module for generating the CPU clock signal, and said stop clock logic asserts the stop clock control signal provided to said clock generator when the signal from the bus bridge and the signal from the CPU module are asserted concurrently.
References Cited (Backward Citations)
US5922075A
Cited
US6272642B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-23 | 2006-03-25 | 2006-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-23 | 2010-03-25 | 2010-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-23 | 2014-03-25 | 2014-09-24 | $7700.00 | Window Closed / Lapsed |