Patent US6455402B2 successfully refreshed from Google Patents.
US6455402B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming retrograde doping file in twin well CMOS device
Assignee: SK Hynix Inc
•
Filing: 2001-03-20
•
Granted: 2002-09-24
•
Expires: 2021-03-20
Abstract
Abstract The method of fabricating a semiconductor device includes the steps of selectively forming an insulating oxide layer in a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate has first and second regions; forming impurity layers having a second conductivity type in the first and second regions of the semiconductor substrate; forming a first mask layer in the second region of the semiconductor substrate; forming impurity layers having the second conductivity type in the first region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies; forming a second mask layer in the first region of the semiconductor substrate; and forming impurity layers having the first conductivity type in the second region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies.
Inventors
- 👤 Joo-Hyong Lee
- 👤 Jeong-Hwan Son
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:42
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/919
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
245 words
A method of fabricating a semiconductor device comprising: selectively forming at least one insulating oxide layer in a semiconductor substrate having a first conductivity type; performing a blanket ion implantation with first dopants having a second conductivity type at a second energy on the entire semiconductor substrate so as to simultaneously form a counter-doped layer of a first retrograde well having the first conductivity type and an upper layer of a second retrograde well having the second conductivity type; performing first serial ion implantations with the first dopants at a first energy and a third energy so as to sequentially form a lower layer and a threshold voltage controlling layer of the second retrograde well, respectively, wherein the first energy is greater than the second energy, and wherein the third energy is smaller than the second energy; and performing second serial ion implantations with second dopants having the first conductivity type at a fourth energy, a fifth energy and a sixth energy so as to sequentially form a lower layer, an upper layer and a threshold voltage controlling layer of the first retrograde well, respectively, wherein the second dopants implanted to form the upper layer of the first retrograde well have a dose greater than that of the first dopants blanket-implanted to form the counter-doped layer of the first retrograde well, such that the first dopants in the counter-doped layer are annihilated by the second dopants in the upper layer of the first retrograde well.
Claim 2
Independent Claim
245 words
A method of fabricating a semiconductor device comprising: selectively forming at least one insulating oxide layer in a semiconductor substrate having a first conductivity type; performing a blanket ion implantation with first dopants having a second conductivity type at a second energy on the entire semiconductor substrate so as to simultaneously form a counter-doped layer of a first retrograde well having the first conductivity type and an upper layer of a second retrograde well having the second conductivity type; performing first serial ion implantations with the first dopants at a first energy and a third energy so as to sequentially form a lower layer and a threshold voltage controlling layer of the second retrograde well, respectively, wherein the first energy is greater than the second energy, and wherein the third energy is smaller than the second energy; and performing second serial ion implantations with second dopants having the first conductivity type at a fourth energy, a fifth energy and a sixth energy so as to sequentially form a lower layer, an upper layer and a threshold voltage controlling layer of the first retrograde well, respectively, wherein the second dopants implanted to form the upper layer of the first retrograde well have a dose greater than that of the first dopants blanket-implanted to form the counter-doped layer of the first retrograde well, such that the first dopants in the counter-doped layer are annihilated by the second dopants in the upper layer of the first retrograde well.
Claim 3
Dependent Claim
23 words
The method as claimed in claim 1 , wherein the first and second retrograde wells each has a junction depth of 1.5 μm.
Claim 4
Dependent Claim
58 words
The method as claimed in claim 1 , wherein the dose of the second dopants implanted to form the upper layer of the first retrograde well is about 6.0×10 12 /cm 2 and wherein the dose of the first dopants blanket-implanted to form the counter-doped layer of the first retrograde well is about 4.0×10 12 /cm 2 .
Claim 5
Dependent Claim
83 words
The method as claimed in claim 1 , further comprising: selectively forming a first mask layer on the semiconductor substrate before performing the first serial ion implantations so as to expose a region where the second retrograde well is formed; removing the first mask layer after performing the first serial ion implantations; and selectively forming a second mask layer on the semiconductor substrate before performing the second serial ion implantations so as to expose a region where the second retrograde well is formed.
Claim 6
Dependent Claim
27 words
The method as claimed in claim 4 , further comprising: annealing the first and second dopants that are implanted via the first and second serial ion implantations.
Claim 7
Dependent Claim
19 words
The method as claimed in claim 5 , wherein the annealing is performed by a rapid thermal annealing apparatus.
References Cited (Backward Citations)
US4661202A
Cited
EP0358246A1
Cited
JPH03173172A
Cited
USRE35613E
Cited
JPH0536917A
Cited
US5763921A
Cited
JP3173172B2
Cited
US5814866A
Cited
US6017785A
Cited
US5795803A
Cited
US6096611A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-23 | 2006-03-25 | 2006-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-23 | 2010-03-25 | 2010-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-23 | 2014-03-25 | 2014-09-24 | $7700.00 | Window Closed / Lapsed |