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Patent US6445077B1 successfully refreshed from Google Patents.
US6445077B1
Expired / Lapsed
US
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Semiconductor chip package
Assignee: Samsung Electronics Co Ltd
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Filing: 2001-06-20
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Granted: 2002-09-03
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Expires: 2021-06-20
Abstract
Abstract A semiconductor chip package includes a semiconductor chip and a substrate on which the semiconductor chip attaches. The semiconductor chip includes center and edge bonding pads. The substrate includes a first window that exposes the center bonding pads, a second window that exposes the edge bonding pads, connection pads around the first and second windows, external terminal pads, and a wiring pattern. The semiconductor chip package further includes bonding wires, an encapsulation body, and external terminals. The bonding wires connect the center and edge bonding pads of the semiconductor chip to the connection pads of the substrate. A method for manufacturing a semiconductor chip package includes: preparing a semiconductor chip having center and edge bonding pads and a substrate, which includes a first window, a second window, connection pads, external terminal pads, and a wiring pattern; attaching the semiconductor chip on the substrate such that the first window exposes the center bonding pads and the second window exposes the edge bonding pads; connecting the first and second bonding pads to corresponding connection pads; encapsulating side surfaces of the semiconductor chip, a portion of the bottom surface of the substrate, the bonding wires, and the connection pads; and forming external terminals on the external terminal pads of the substrate. The encapsulating includes a first encapsulation of the side surfaces of the semiconductor chip and a portion of the bottom surface of the substrate and a second encapsulation of the bonding wires and the connection pads.
Inventors
- 👤 Ill Heung Choi
- 👤 Young Hee Song
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:46
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W72/00; H10W72/071; H10W72/90; H10W74/00; H10W74/10; H10W74/111; H10W72/073; H10W72/075; H10W72/20; H10W72/29; H10W72/50; H10W72/541; H10W72/5445; H10W72/5449; H10W72/851; H10W72/853; H10W72/865; H10W72/931; H10W72/932; H10W74/131; H10W74/142; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
189 words
A semiconductor chip package comprising: a semiconductor chip having a plurality of center bonding pads formed on a surface of the semiconductor chip in a central area of the surface and a plurality of edge bonding pads formed along edges of the surface of the semiconductor chip; a substrate having the semiconductor chip attached to a surface of the substrate, the substrate comprising: a first window that exposes the center bonding pads; a second window that exposes the edge bonding pads; a plurality of connection pads around the first and second windows on a top surface of the substrate; a plurality of external terminal pads on the top surface; and a wiring pattern that connects the connection pads to the external terminal pads; a plurality of bonding wires that connect the center and edge bonding pads of the semiconductor chip to the connection pads of the substrate; an encapsulation body that encapsulates side surfaces of the semiconductor chip, a portion of the bottom surface of the substrate, the bonding wires, and the connection pads; and a plurality of external terminals formed on the external terminal pads of the substrate.
Claim 2
Dependent Claim
189 words
A semiconductor chip package comprising: a semiconductor chip having a plurality of center bonding pads formed on a surface of the semiconductor chip in a central area of the surface and a plurality of edge bonding pads formed along edges of the surface of the semiconductor chip; a substrate having the semiconductor chip attached to a surface of the substrate, the substrate comprising: a first window that exposes the center bonding pads; a second window that exposes the edge bonding pads; a plurality of connection pads around the first and second windows on a top surface of the substrate; a plurality of external terminal pads on the top surface; and a wiring pattern that connects the connection pads to the external terminal pads; a plurality of bonding wires that connect the center and edge bonding pads of the semiconductor chip to the connection pads of the substrate; an encapsulation body that encapsulates side surfaces of the semiconductor chip, a portion of the bottom surface of the substrate, the bonding wires, and the connection pads; and a plurality of external terminals formed on the external terminal pads of the substrate.
Claim 3
Dependent Claim
18 words
The semiconductor chip package in claim 1 , wherein an adhesive attaches the semiconductor chip to the substrate.
Claim 4
Dependent Claim
21 words
The se miconductor chip package in claim 1 , wherein the center bonding pads are aligned in a plurality of rows.
Claim 5
Dependent Claim
20 words
The semiconductor chip package in claim 1 , wherein the edge bonding pads are aligned in a plurality of rows.
Claim 6
Dependent Claim
15 words
The semiconductor chip package in claim 1 , wherein the external terminals are solder balls.
Claim 7
Dependent Claim
54 words
The semiconductor chip package in claim 1 , wherein the encapsulation body comprises a first encapsulation portion and a second encapsulation portion, the first encapsulation portion encapsulating the side surfaces of the semiconductor chip and the bottom surface of the substrate, and the second encapsulation portion encapsulating the bonding wires and the connection pads.
Claim 8
Dependent Claim
19 words
The semiconductor chip package in claim 6 , wherein the first encapsulation portion is formed by potting an encapsulant.
Claim 9
Dependent Claim
19 words
The semiconductor chip package in claim 6 , wherein the second encapsulation portion is formed by potting an encapsulant.
Claim 10
Dependent Claim
18 words
The semiconductor chip package in claim 6 , wherein the second encapsulation portion is formed by a transfer-molding.
Claim 11
Dependent Claim
26 words
The semiconductor chip package in claim 1 , wherein a portion of an edge of the semiconductor chip is within a boundary of the second window.
Claim 12
Dependent Claim
29 words
The semiconductor chip package in claim 1 , wherein the center bonding pads and the edge bonding pads are aligned in rows, and further wherein the rows are parallel.
Claim 13
Dependent Claim
29 words
The semiconductor chip package in claim 1 , wherein the center bonding pads and the edge bonding pads are aligned in rows, and further wherein the rows are perpendicular.
Claim 14
Dependent Claim
20 words
The semiconductor chip package in claim 1 , wherein the first and second windows are integrated into a single window.
Claim 15
Dependent Claim
16 words
The semiconductor chip package in claim 1 , wherein the substrate is a printed circuit board.
Claim 16
Dependent Claim
15 words
The semiconductor chip package in claim 1 , wherein the substrate comprises a flexible tape.
Claim 17
Dependent Claim
30 words
The semiconductor chip package in claim 15 , wherein the flexible tape is a TAB tape, wherein a plurality of beam leads of the TAB tape replaces the bonding wires.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-02 | 2006-03-04 | 2006-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-02 | 2010-03-04 | 2010-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-02 | 2014-03-04 | 2014-09-03 | $7700.00 | Window Closed / Lapsed |