Patent US6442746B1 successfully refreshed from Google Patents.
US6442746B1
Expired / Lapsed
US
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Preventing damaging of low voltage processor in high voltage system
Assignee: Intel Corp
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Filing: 1999-12-21
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Granted: 2002-08-27
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Expires: 2019-12-21
Abstract
Abstract A method and apparatus for protecting a low voltage processor inserted in a high voltage processor connector includes a circuit that determines whether power can be safely asserted to the connector, or whether power should be disabled due to a non-compliant processor. A method enables power to the connector upon a determination that a compliant processor, a termination card, or an empty connector is present.
Inventors
- 👤 Patrick D. James
- 👤 Son H. Lam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:07
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
87 words
A method for preventing damage to a low voltage processor inserted into a high voltage processor system, comprising: determining whether a high voltage processor is present in the processor slot by logically combining a high voltage enable signal and a power enable signal from the processor; determining whether a termination card is present in the processor slot; determining whether the processor slot is empty; and setting a power on okay signal on determining that a high voltage processor, a termination card, or an empty slot is present.
Claim 2
Independent Claim
87 words
A method for preventing damage to a low voltage processor inserted into a high voltage processor system, comprising: determining whether a high voltage processor is present in the processor slot by logically combining a high voltage enable signal and a power enable signal from the processor; determining whether a termination card is present in the processor slot; determining whether the processor slot is empty; and setting a power on okay signal on determining that a high voltage processor, a termination card, or an empty slot is present.
Claim 3
Dependent Claim
16 words
The method of claim 1 , wherein the combining is performed in an exclusive NOR gate.
Claim 4
Dependent Claim
30 words
The method of claim 1 , wherein determining whether the processor slot is empty comprises logically combining a high voltage enable signal and a power enable signal from the processor.
Claim 5
Dependent Claim
56 words
The method of claim 1 , wherein determining whether a termination card is installed comprises logically combining a core identification bit 3 signal and a core voltage identification bit 4 signal complement from the processor, and a complement of a logical combination of a high voltage enable signal and a power enable signal from the processor.
Claim 6
Dependent Claim
29 words
The method of claim 4 , wherein the logical combination of the core identification bit 3 and the core identification bit 4 complement is performed in an AND gate.
Claim 7
Dependent Claim
15 words
The method of claim 1 , wherein the determinations are made in a different order.
Claim 8
Dependent Claim
153 words
A circuit, comprising: a connector to receive an electrical component; and connector logic operatively electrically connected to the connector for logically combining signals from the component to determine the identity of the component, the connector logic comprising an exclusive or gate having two inputs connectable to a high voltage enable signal and a power enable signal; an inverter connected to the output of the exclusive or gate; a second inverter with an input connectable to a core identification bit 4 signal slot; an and gate having three inputs, the first input connected to the output of the inverter, the second input connected to the output of the second inverter, and the third input connectable to a core identification bit 3 signal slot; and an or gate having two inputs, the first input connected to the output of the exclusive or gate, and the second input connected to the output of the and gate.
Claim 9
Dependent Claim
153 words
A circuit, comprising: a connector to receive an electrical component; and connector logic operatively electrically connected to the connector for logically combining signals from the component to determine the identity of the component, the connector logic comprising an exclusive or gate having two inputs connectable to a high voltage enable signal and a power enable signal; an inverter connected to the output of the exclusive or gate; a second inverter with an input connectable to a core identification bit 4 signal slot; an and gate having three inputs, the first input connected to the output of the inverter, the second input connected to the output of the second inverter, and the third input connectable to a core identification bit 3 signal slot; and an or gate having two inputs, the first input connected to the output of the exclusive or gate, and the second input connected to the output of the and gate.
Claim 10
Dependent Claim
33 words
The circuit of claim 7 , wherein the connector logic is configured to assert a signal to power to the connector upon a determination that power may safely be asserted to the connector.
Claim 11
Dependent Claim
37 words
The circuit of claim 7 , wherein the connector logic is configured to determine whether the connector is empty, or whether the connector contains a high voltage compliant processor, a termination card or a non-high voltage processor.
Claim 12
Independent Claim
51 words
A method comprising: determining whether power to a processor connector may be safely asserted, including determining whether a high-voltage processor is installed by logically combining a high voltage enable signal and a power enable signal; and asserting power to the processor connector on a determination that power may be safely asserted.
Claim 13
Independent Claim
51 words
A method comprising: determining whether power to a processor connector may be safely asserted, including determining whether a high-voltage processor is installed by logically combining a high voltage enable signal and a power enable signal; and asserting power to the processor connector on a determination that power may be safely asserted.
Claim 14
Independent Claim
51 words
A method comprising: determining whether power to a processor connector may be safely asserted, including determining whether the processor connector is empty by logically combining a high voltage enable signal and a power enable signal; and asserting power to the processor connector on a determination that power may be safely asserted.
Claim 15
Independent Claim
51 words
A method comprising: determining whether power to a processor connector may be safely asserted, including determining whether the processor connector is empty by logically combining a high voltage enable signal and a power enable signal; and asserting power to the processor connector on a determination that power may be safely asserted.
Claim 16
Independent Claim
75 words
A method comprising: determining whether power to a processor connector may be safely asserted, including determining whether a termination card is installed in the processor connector by logically combining a core identification bit 3 signal, a core identification bit 4 complement, and a complement of a logical combination of a high voltage enable signal and a power enable signal; and asserting power to the processor connector on a determination that power may be safely asserted.
Claim 17
Independent Claim
75 words
A method comprising: determining whether power to a processor connector may be safely asserted, including determining whether a termination card is installed in the processor connector by logically combining a core identification bit 3 signal, a core identification bit 4 complement, and a complement of a logical combination of a high voltage enable signal and a power enable signal; and asserting power to the processor connector on a determination that power may be safely asserted.
Claim 18
Dependent Claim
138 words
A connector for a processor, comprising: a plurality of processor contacts configured to accept a connector component; a circuit for enabling power to the connector upon a determination that the component is high voltage compliant, wherein the circuit comprises connector logic for logically combining signals from the component installed in the connector to determine the identity of the component, the connector logic including: first logic for combining a high voltage enable signal and a power enable signal; second logic for inverting the output of the first logic; third logic for inverting a core identification bit 4 signal; fourth logic for combining the output of the second logic, the output of the second logic, and a core identification bit 3 signal; and fifth logic for combining the output of the first logic and the output of the fourth logic.
Claim 19
Dependent Claim
138 words
A connector for a processor, comprising: a plurality of processor contacts configured to accept a connector component; a circuit for enabling power to the connector upon a determination that the component is high voltage compliant, wherein the circuit comprises connector logic for logically combining signals from the component installed in the connector to determine the identity of the component, the connector logic including: first logic for combining a high voltage enable signal and a power enable signal; second logic for inverting the output of the first logic; third logic for inverting a core identification bit 4 signal; fourth logic for combining the output of the second logic, the output of the second logic, and a core identification bit 3 signal; and fifth logic for combining the output of the first logic and the output of the fourth logic.
Claim 20
Dependent Claim
15 words
The connector of claim 13 , wherein the first logic is an exclusive NOR gate.
Claim 21
Dependent Claim
14 words
The connector of claim 13 , wherein the fourth logic is an AND gate.
Claim 22
Dependent Claim
14 words
The connector of claim 13 , wherein the fifth logic is an OR gate.
Claim 23
Dependent Claim
149 words
A motherboard, comprising: a processor connector; a power supply operatively electrically connected to the motherboard and the processor connector; and a circuit for enabling power to the connector upon a determination that a termination card or a high voltage compliant processor is installed in the connector slot, the circuit including: connector logic for logically combining signals from the component installed in the connector to determine the identity of the component, the connector logic including: first logic for combining a high voltage enable signal and a power enable signal; second logic for inverting the output of the first logic; third logic for inverting a core identification bit 4 signal; fourth logic for combining the output of the second logic, the output of the second logic, and a core identification bit 3 signal; and fifth logic for combining the output of the first logic and the output of the fourth logic.
Claim 24
Dependent Claim
149 words
A motherboard, comprising: a processor connector; a power supply operatively electrically connected to the motherboard and the processor connector; and a circuit for enabling power to the connector upon a determination that a termination card or a high voltage compliant processor is installed in the connector slot, the circuit including: connector logic for logically combining signals from the component installed in the connector to determine the identity of the component, the connector logic including: first logic for combining a high voltage enable signal and a power enable signal; second logic for inverting the output of the first logic; third logic for inverting a core identification bit 4 signal; fourth logic for combining the output of the second logic, the output of the second logic, and a core identification bit 3 signal; and fifth logic for combining the output of the first logic and the output of the fourth logic.
Claim 25
Dependent Claim
15 words
The motherboard of claim 17 , wherein the circuit is contained within the processor connector.
References Cited (Backward Citations)
US5872983A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-26 | 2006-02-25 | 2006-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-26 | 2010-02-25 | 2010-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-26 | 2014-02-25 | 2014-08-27 | $7700.00 | Window Closed / Lapsed |