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US6442737B1
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Method of generating an optimal clock buffer set for minimizing clock skew in balanced clock trees
Assignee: Bell Semiconductor LLC
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Filing: 2001-06-06
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Granted: 2002-08-27
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Expires: 2021-06-06
Abstract
Abstract The present invention has application to final balancing of an initial balanced clock tree. In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each level of a balanced clock tree. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit. In one such embodiment, a method of balancing a clock tree includes the steps of receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays for replacing at least one clock buffer in the balanced clock tree with a clock buffer delay selected from the minimum set of clock buffer delays such that the difference between the optimum delay and the clock buffer delay is less than or equal to the selected skew limit; and generating as output the minimum set of clock buffer delays.
Inventors
- 👤 Alexander Tetelbaum
- 👤 Ruben Molina, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:46
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
92 words
A method of generating a minimum set of delays for balancing a clock tree comprising the steps of: (a) receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; (b) generating a minimum set of clock buffer delays such that the difference between an optimum delay and one of the clock buffer delays is less than or equal to the selected skew limit for each clock buffer in the initial balanced clock tree; and (c) generating as output the minimum set of clock buffer delays.
Claim 2
Independent Claim
92 words
A method of generating a minimum set of delays for balancing a clock tree comprising the steps of: (a) receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; (b) generating a minimum set of clock buffer delays such that the difference between an optimum delay and one of the clock buffer delays is less than or equal to the selected skew limit for each clock buffer in the initial balanced clock tree; and (c) generating as output the minimum set of clock buffer delays.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein step (b) comprises including the minimum buffer delay in the minimum set of clock buffer delays.
Claim 4
Dependent Claim
40 words
The method of claim 1 wherein step (b) comprises calculating each of the minimum set of clock buffer delays substantially equal to the sum of the minimum buffer delay and an integer multiple of two times the selected skew limit.
Claim 5
Dependent Claim
99 words
The method of claim 1 wherein step (b) further comprises the steps of: (b1) initializing a buffer delay value D BUF to the minimum buffer delay; (b2) including the buffer delay value D BUF in the minimum set of clock buffer delays; (b3) if the difference between the delay value D BUF minus the minimum clock buffer delay and the maximum level skew limit is less than or equal to the selected skew limit, then continuing from step (d); otherwise (b4) incrementing the buffer delay value D BUF by twice the selected skew limit and continuing from step (b2).
Claim 6
Dependent Claim
108 words
A computer program product comprising: a medium for embodying a computer program for input to a computer; and a computer program embodied in the medium for causing the computer to perform the following functions: (a) receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; (b) generating a minimum set of clock buffer delays such that the difference between the optimum delay and one of the clock buffer delays is less than or equal to the selected skew limit for each clock buffer in the initial balanced clock tree; and (c) generating as output the minimum set of clock buffer delays.
Claim 7
Dependent Claim
108 words
A computer program product comprising: a medium for embodying a computer program for input to a computer; and a computer program embodied in the medium for causing the computer to perform the following functions: (a) receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; (b) generating a minimum set of clock buffer delays such that the difference between the optimum delay and one of the clock buffer delays is less than or equal to the selected skew limit for each clock buffer in the initial balanced clock tree; and (c) generating as output the minimum set of clock buffer delays.
Claim 8
Dependent Claim
24 words
The computer program product of claim 5 wherein step (b) comprises including the minimum buffer delay in the minimum set of clock buffer delays.
Claim 9
Dependent Claim
42 words
The computer program product of claim 5 wherein step (b) comprises calculating each of the minimum set of clock buffer delays substantially equal to the sum of the minimum buffer delay and an integer multiple of two times the selected skew limit.
Claim 10
Dependent Claim
101 words
The computer program product of claim 5 wherein step (b) further comprises the steps of: (b1) initializing a buffer delay value D BUF to the minimum buffer delay; (b2) including the buffer delay value D BUF in the minimum set of clock buffer delays; (b3) if the difference between the delay value D BUF minus the minimum clock buffer delay and the maximum level skew limit is less than or equal to the selected skew limit, then continuing from step (d); otherwise (b4) incrementing the buffer delay value D BUF by twice the selected skew limit and continuing from step (b2).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-26 | 2006-02-25 | 2006-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-26 | 2010-02-25 | 2010-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-26 | 2014-02-25 | 2014-08-27 | $7700.00 | Window Closed / Lapsed |