Method and apparatus for detecting the type of interface to which a peripheral device is connected

Claim 2

A peripheral device connectable to a computer having one of a first interface and a second interface, the first interface communicating with the peripheral device over a differential data connection including a first data conductor and a second data conductor connected to a first voltage potential with first and second resistive elements, respectively, and the second interface communicating with the peripheral device over a single ended data connection, including a first data conductor and a clock conductor pulled to a second voltage potential by third and fourth resistive elements, respectively, the peripheral device comprising: first and second communication conductors configured for connection to the first and second data conductors in the differential data connection when the computer includes the first interface, and configured for connection to the first data conductor in the single ended data connection and the clock conductor when the computer includes the second interface; an interface detection component, coupled to the first and second communication conductors, including connection elements selectable connecting the first and second communication conductors to a predetermined voltage potential and a signal detector configured to detect signal levels on the first and second communication conductors to detect which of the first and second interfaces the peripheral device is connected to when the connection elements are deselected to selectively disconnect the first and second communication conductors from the predetermined voltage potential and to provide a connection output indicative of the detected interface; and a controller component, coupled to the interface detection component, configured to communicate between the peripheral device and the computer over the first and second communication conductors according to a protocol corresponding to the detected interface based on the connection output.

Claim 3

The peripheral device of claim 1 wherein the interface detection component comprises: a fifth resistive element; a sixth resistive element; and wherein the connection elements include: a first selectable connection element selectively connecting the first communication conductor to the predetermined voltage potential, which comprises a third voltage potential, through the fifth resistive element; and a second selectable connection element selectively connecting the second communication conductor to the third voltage potential through the sixth resistive element.

Claim 4

The peripheral device of claim 2 wherein the second and third voltage potentials are associated with a first logic level.

Claim 5

The peripheral device of claim 3 wherein the interface connection component is configured to deselect the first and second selectable connection elements to disconnect the first and second communication conductors from the third voltage potential upon power-up of the peripheral device.

Claim 6

The peripheral device of claim 4 wherein the signal detector is configured to detect signal levels on the first and second communication conductors upon power-up of the peripheral device, when the first and second selectable connection elements are deselected.

Claim 7

The peripheral device of claim 5 wherein the signal detector is configured to (a) provide the connection output indicative of connection to the second interface when the signal level corresponding to at least one of the first and second communication conductors is at the first logic level.

Claim 8

The peripheral device of claim 6 wherein the interface detection component is configured to select the first selectable connection element and deselect the second connection element and wherein the signal detector is configured to provide the connection output indicative of connection to the first interface when the signal level corresponding to the first communication conductor is at a first logic level corresponding to the second voltage potential.

Claim 9

The peripheral device of claim 6 wherein the interface detection component is configured to (b) select the first selectable connection element and deselect the second connection element , and if neither of the first and second communication conductors is at the first logic level, deselect the first selectable connection element and revert to step (a).

Claim 10

The peripheral device of claim 8 wherein the signal detector is configured to provide the connection output indicative of connection to the first interface when the signal level corresponding to the first communication conductor is at the first logic level.

Claim 11

The peripheral device of claim 8 wherein the interface detection component is configured to deselect the first selectable connection element and deselect the second connection element and wherein the signal detector is configured to provide the connection output indicative of connection to the first interface when the signal level corresponding to the first communication conductor is at the second logic level and to provide the connection output indicative of connection to the second interface when the signal level corresponding to at least one of the first and second communication conductors is at the first logic level.

Claim 12

The peripheral device of claim 10 wherein the first logic level corresponds to a logic one and wherein the second logic level corresponds to a logic zero.

Claim 13

The peripheral device of claim 1 wherein the controller component comprises: a first controller configured to control communication according to a first protocol corresponding to the first interface; and a second controller configured to control communication according to a second protocol corresponding to the second interface.

Claim 14

The peripheral device of claim 12 wherein the first controller is coupled to differential data pins providing differential data signals, the differential data pins being coupled to the first and second communication conductors.

Claim 15

The peripheral device of claim 13 wherein the second controller is coupled to first and second input/output (I/O) pins providing a first data signal and a clock signal, the first and second I/O pins being coupled to the first and second communication conductors.

Claim 16

The peripheral device of claim 14 and further comprising: a first switch coupled between a first of the differential data pins and the first communication conductor, the controller component being configured to selectively close the first switch when the interface detection component provides the connection output indicative of the detected interface being the first interface.

Claim 17

The peripheral device of claim 15 wherein the controller component is configured to open the first switch when the interface detection component provides the connection output indicative of the detected interface being the second interface.

Claim 18

The peripheral device of claim 16 and further comprising: a second switch coupled between a second of the differential data pins and the second communication conductor, the controller component being configured to selectively close the second switch when the interface detection component provides the connection output indicative of the detected interface being the first interface.

Claim 19

The peripheral device of claim 17 wherein the controller component is configured to open the second switch when the interface detection component provides the connection output indicative of the detected interface being the second interface.

Claim 20

The peripheral device of claim 15 wherein the second controller is configured to provide a high impedance signal on the first and second I/O pins when the interface detection component provides the connection output indicative of the detected interface being the first interface.

Claim 21

The peripheral device of claim 19 and further comprising: first and second resistive elements coupled between the first and second communication conductors and third and fourth I/O pins, respectively, wherein the controller component is configured to provide a signal on the third and fourth I/O pins at a high impedance state when the interface detection. component provides the connection output indicative of the detected interface being the first interface and at a voltage level when the interface detection component provides the connection output indicative of the detected interface being the second interface.

Claim 22

A computer readable medium for use in a peripheral device connectable to a computer, the computer having one of a first interface and a second interface, the first interface communicating with the peripheral device over a differential data connection including a first data conductor and a second data conductor, and the second interface communicating with the peripheral device over a single ended data connection, including a first data conductor, and a clock conductor, the peripheral device including first and second communication conductors configured for connection to the first and second data conductors in the differential data connection when the computer includes the first interface, and configured for connection to the first data conductor in the single ended data connection and the clock conductor when the computer includes the second interface, the computer readable medium including instructions stored thereon which when executed by the peripheral device causes the peripheral device to execute the steps of: (a) detecting which of the first and second interfaces the peripheral device is connected to, by: (a)(1) disconnecting the first and second communication conductors from a predetermined voltage potential; (a)(2) determining whether either of the first and second communication conductors is at a first logic-level associated with a first voltage potential; if so, (a)(3) determining that the peripheral device is connected to the second interface; (a)(4) if neither of the first and second communication conductors is at the first logic level in step (a)(2), connecting the first communication conductor to the first voltage potential through a first resistive element; and (a)(5) determining whether either of the first and second communication conductors is at the first logic level; and if not (a)(6), returning to step (a)(1); (b) communicating with the computer over the first and second communication conductors according to a protocol corresponding to the detected interface.

Claim 23

A computer readable medium for use in a peripheral device connectable to a computer, the computer having one of a first interface and a second interface, the first interface communicating with the peripheral device over a differential data connection including a first data conductor and a second data conductor, and the second interface communicating with the peripheral device over a single ended data connection, including a first data conductor, and a clock conductor, the peripheral device including first and second communication conductors configured for connection to the first and second data conductors in the differential data connection when the computer includes the first interface, and configured for connection to the first data conductor in the single ended data connection and the clock conductor when the computer includes the second interface, the computer readable medium including instructions stored thereon which when executed by the peripheral device causes the peripheral device to execute the steps of: (a) detecting which of the first and second interfaces the peripheral device is connected to, by: (a)(1) disconnecting the first and second communication conductors from a predetermined voltage potential; (a)(2) determining whether either of the first and second communication conductors is at a first logic-level associated with a first voltage potential; if so, (a)(3) determining that the peripheral device is connected to the second interface; (a)(4) if neither of the first and second communication conductors is at the first logic level in step (a)(2), connecting the first communication conductor to the first voltage potential through a first resistive element; and (a)(5) determining whether either of the first and second communication conductors is at the first logic level; and if not (a)(6), returning to step (a)(1); (b) communicating with the computer over the first and second communication conductors according to a protocol corresponding to the detected interface.

Claim 24

The computer readable medium of claim 21 wherein detecting (a) further comprises: (a)(7) if the first communication conductor is at the first logic level, determining that the peripheral device is connected to the first interface.

Claim 25

The computer readable medium of claim 22 wherein detecting (a) further comprises: (a)(8) if either the first or second communication conductors are at the first logic level, disconnecting the first communication conductor from the first voltage potential; and (a)(9) determining whether either of the first and second communication conductors are at the first voltage potential.

Claim 26

The computer readable medium of claim 23 wherein detecting (a) further comprises: if either of the first and second communication conductors are at the first logic level in step (a)(9), (a)(10) determining that the peripheral device is connected to the second interface; and otherwise, (a)(11) determining that the peripheral device is connected to the first interface.

Claim 29

The method of claim 25 wherein detecting (a) further comprises: (a)(7) if the first communication conductor is at the first logic level, determining that the peripheral device is connected to the first interface.

Claim 30

The method of claim 25 wherein detecting (a) further comprises: (a)(8) if either the first or second communication conductors is at the first logic level, disconnecting the first communication conductor from the first voltage potential; and (a)(9) determining whether either of the first and second communication conductors are at the first voltage potential.

Claim 31

The method of claim 27 wherein detecting (a) further comprises: if either of the first and second communication conductors are at the first logic level in step (a)(9), (a)(10) determining that the peripheral device is connected to the second interface; and otherwise, (a)(11) determining that the peripheral device is connected to the first interface.

Claim 32

A peripheral device connectable to a computer having one of a first interface and a second interface, the first interface communicating with the peripheral device over a differential data connection including a first data conductor and a second data conductor connected to a first voltage potential with first and second resistive elements, respectively, and the second interface communicating with the peripheral device over a single ended data connection, including a first data conductor, and a clock conductor pulled to a second voltage potential by third and fourth resistive elements, respectfully, the peripheral device comprising: first and second communication conductors configured for connection to the first and second data conductors in the differential data connection when the computer includes the first interface, and configured for connection to the clock conductor and the first data conductor in the single ended data connection when the computer includes the second interface; an interface detection component, coupled to the first and second communication conductors, including connection elements selectably connecting the first and second communication conductors to a predetermined voltage potential and a signal detector configured to detect signal levels on the first and second communication conductors when the connection elements are deselected to selectively disconnect the first and second communication conductors from the predetermined voltage potential to detect which of the first and second interfaces the peripheral device is connected to and to provide a connection output indicative of the detected interface; and a controller component, coupled to the interface detection component, configured to communicate between the peripheral device and the computer over the first and second communication conductors according to a protocol corresponding to the detected interface based on the connection output.

Claim 33

A peripheral device connectable to a computer having one of a first interface and a second interface, the first interface communicating with the peripheral device over a differential data connection including a first data conductor and a second data conductor connected to a first voltage potential with first and second resistive elements, respectively, and the second interface communicating with the peripheral device over a single ended data connection, including a first data conductor, and a clock conductor pulled to a second voltage potential by third and fourth resistive elements, respectfully, the peripheral device comprising: first and second communication conductors configured for connection to the first and second data conductors in the differential data connection when the computer includes the first interface, and configured for connection to the clock conductor and the first data conductor in the single ended data connection when the computer includes the second interface; an interface detection component, coupled to the first and second communication conductors, including connection elements selectably connecting the first and second communication conductors to a predetermined voltage potential and a signal detector configured to detect signal levels on the first and second communication conductors when the connection elements are deselected to selectively disconnect the first and second communication conductors from the predetermined voltage potential to detect which of the first and second interfaces the peripheral device is connected to and to provide a connection output indicative of the detected interface; and a controller component, coupled to the interface detection component, configured to communicate between the peripheral device and the computer over the first and second communication conductors according to a protocol corresponding to the detected interface based on the connection output.

Claim 34

The peripheral device of claim 29 wherein the interface detection component comprises; a fifth resistive element; a sixth resistive element; and wherein the connection elements include: a first selectable connection element selectively connecting the first communication conductor to the predetermined voltage potential, which comprises a third voltage potential, through the fifth resistive element; and a second selectable connection element selectively connecting the second communication conductor to the third voltage potential through the sixth resistive element.

Claim 35

The peripheral device of claim 30 wherein the second and third voltage potentials are associated with a first logic level.

Claim 36

The peripheral device of claim 31 wherein the interface connection component is configured to deselect the first and second selectable connection elements to disconnect the first and second communication conductors from the third voltage potential upon power-up of the peripheral device.

Claim 37

The peripheral device of claim 32 wherein the signal detector is configured to detect signal levels on the first and second communication conductors upon power-up of the peripheral device, when the first and second selectable connection elements are deselected.

Claim 38

The peripheral device of claim 33 wherein the signal detector is configured to (a) provide the connection output indicative of connection to the second interface when the signal level corresponding to at least one of the first and second communication conductors is at the first logic level.

Claim 39

The peripheral device of claim 34 wherein the interface detection component is configured to select the first selectable connection element and deselect the second connection element and wherein the signal detector is configured to deselect the first selectable connection and revert to step (a) when the signal level corresponding to the first communication conductor is at a second logic level corresponding to the first voltage potential.

Claim 40

The peripheral device of claim 34 wherein the interface detection component is configured to (b) select the first selectable connection element and deselect the second connection element and if neither one of the first and second communication conductors is at the first logic level, deselect the first selectable connection element and revert to step (a).

Claim 41

The peripheral device of claim 36 wherein the signal detector is configured to provide the connection output indicative of connection to the first interface when the signal level corresponding to the first communication conductor is at the first logic level.

Claim 42

The peripheral device of claim 36 wherein the interface detection component is configured to deselect the first selectable connection element and deselect the second connection element and wherein the signal detector is configured to provide the connection output indicative of connection to the first interface when the signal level corresponding to the first communication conductor is at the second logic level and to provide the connection output indicative of connection to the second interface when the signal level corresponding to at least one of the first and second communication conductors is at the| first logic level.

Claim 43

The peripheral device of claim 38 wherein the first logic level corresponds to a logic one and wherein the second logic level corresponds to a logic zero.

Claim 44

The peripheral device of claim 29 wherein the controller component comprises: a first controller configured to control communication according to a first protocol corresponding to the first interface; and a second controller configured to control communication according to a second protocol corresponding to the second interface.

Claim 45

The peripheral device of claim 40 wherein the first controller is coupled to differential data pins providing differential data signals, the differential data pins being coupled to the first and second communication conductors.

Claim 46

The peripheral device of claim 41 wherein the second controller is coupled to first and second input/output (I/O) pins providing a clock signal and a first data signal, the first and second I/O pins being coupled to the first and second communication conductors.

Claim 47

The peripheral device of claim 42 and further comprising: a first switch coupled between a first of the differential data pins and the first communication conductor, the controller component being configured to selectively close the first switch when the interface detection component provides the connection output indicative of the detected interface being the first interface.

Claim 48

The peripheral device of claim 43 wherein the controller component is configured to open the first switch when the interface detection component provides the connection output indicative of the detected interface being the second interface.

Claim 49

The peripheral device of claim 44 and further comprising: a second switch coupled between a second of the differential data pins and the second communication conductor, the controller component being configured to selectively close the second switch when the interface detection component provides the connection output indicative of the detected interface being the first interface.

Claim 50

The peripheral device of claim 45 wherein the controller component is configured to open the second switch when the interface detection component provides the connection output indicative of the detected interface being the second interface.

Claim 51

The peripheral device of claim 43 wherein the second controller is configured to provide a high impedance signal on the first and second I/O pins when the interface detection component provides the connection output indicative of the detected interface being the first interface.

Claim 52

The peripheral device of claim 47 and further comprising: first and second resistive elements coupled between the first and second communication conductors and third and fourth I/O pins, respectively, wherein the controller component is configured to provide a signal on the third and fourth I/O pins at a high impedance state when the interface detection component provides the connection output indicative of the detected interface being the first interface and at a voltage level when the interface detection component provides the connection output indicative of the detected interface being the second interface.

Claim 53

A computer readable medium for use in a peripheral device connectable to a computer, the computer having one of a first interface and a second interface, the first interface communicating with the peripheral device over a differential data connection including a first data conductor and a second data conductor, and the second interface communicating with the peripheral device over a single ended data connection, including a first data conductor, and a clock conductor, the peripheral device including first and second communication conductors configured for connection to the first and second data conductors in the differential data connection when the computer includes the first interface, and configured for connection to the clock conductor and the first data conductor in the single ended data connection when the computer includes the second interface, the computer readable medium including instructions stored thereon which when executed by the peripheral device causes the peripheral device to execute the steps of: (a) detecting which of the first and second interfaces the peripheral device is connected to, by: (a)(1) disconnecting the first and second communication conductors from a predetermined voltage potential; (a)(2) determining whether either of the first and second communication conductors is at a first logic level associated with a first voltage potential; if so, (a)(3) determining that the peripheral device is connected to the second interface; (a)(4) if neither of the first and second communication conductors is at the first logic level in step (a)(2), connecting the first communication conductor to the first voltage potential through a first resistive element; (a)(5) determining whether either of the first and second communication conductors is at the first logic level; and if not, (a)(6) returning to step (a)(1); and (b) communicating with the computer over the first and second communication conductors according to a protocol corresponding to the detected interface.

Claim 54

A computer readable medium for use in a peripheral device connectable to a computer, the computer having one of a first interface and a second interface, the first interface communicating with the peripheral device over a differential data connection including a first data conductor and a second data conductor, and the second interface communicating with the peripheral device over a single ended data connection, including a first data conductor, and a clock conductor, the peripheral device including first and second communication conductors configured for connection to the first and second data conductors in the differential data connection when the computer includes the first interface, and configured for connection to the clock conductor and the first data conductor in the single ended data connection when the computer includes the second interface, the computer readable medium including instructions stored thereon which when executed by the peripheral device causes the peripheral device to execute the steps of: (a) detecting which of the first and second interfaces the peripheral device is connected to, by: (a)(1) disconnecting the first and second communication conductors from a predetermined voltage potential; (a)(2) determining whether either of the first and second communication conductors is at a first logic level associated with a first voltage potential; if so, (a)(3) determining that the peripheral device is connected to the second interface; (a)(4) if neither of the first and second communication conductors is at the first logic level in step (a)(2), connecting the first communication conductor to the first voltage potential through a first resistive element; (a)(5) determining whether either of the first and second communication conductors is at the first logic level; and if not, (a)(6) returning to step (a)(1); and (b) communicating with the computer over the first and second communication conductors according to a protocol corresponding to the detected interface.

Claim 55

The computer readable medium of claim 49 wherein detecting (a) further comprises: (a)(7) if either the first or second communication conductors are at the first logic level, disconnecting the first communication conductor from the first voltage potential; and (a)(8) determining whether either of the first and second communication conductors are at the first voltage potential.

Claim 56

The computer readable medium of claim 50 wherein detecting (a) further comprises: if either of the first and second communication conductors are at the first logic level in step (a)(8), (a)(9) determining that the peripheral device is connected to the second interface; and otherwise, (a)(10) determining that the peripheral device is connected to the first interface.