Patent US6436748B1 successfully refreshed from Google Patents.
US6436748B1
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US
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Method for fabricating CMOS transistors having matching characteristics and apparatus formed thereby
Assignee: Aptina Imaging Corp
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Filing: 1999-08-31
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Granted: 2002-08-20
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Expires: 2019-08-31
Abstract
Abstract A method for forming NMOS and PMOS transistors that includes cutting a substrate along a (111) orientation and fabricating deep sub-micron NMOS and PMOS transistors thereon. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such a memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.
Inventors
- 👤 Leonard Forbes
- 👤 Wendell P. Noble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:15
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D62/00; H10D62/40; H10D62/405; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
62 words
A method for fabricating an integrated circuit structure, said method comprising the steps of: providing a substrate having a (111) surface; and fabricating at least one each of PMOS and NMOS transistors on said (111) surface; wherein said PMOS and NMOS transistors are fabricated at less than 0.5 micron, have substantially matching switching characteristics and occupy substantially equal areas of said substrate.
Claim 2
Independent Claim
62 words
A method for fabricating an integrated circuit structure, said method comprising the steps of: providing a substrate having a (111) surface; and fabricating at least one each of PMOS and NMOS transistors on said (111) surface; wherein said PMOS and NMOS transistors are fabricated at less than 0.5 micron, have substantially matching switching characteristics and occupy substantially equal areas of said substrate.
Claim 3
Dependent Claim
30 words
A method as in claim 1 , wherein said at least one each of said fabricated PMOS and NMOS transistors are paired to form at least one CMOS transistor pair.
Claim 4
Dependent Claim
14 words
A method as in claim 1 , wherein said substrate is a silicon substrate.
Claim 5
Dependent Claim
62 words
An integrated circuit structure, comprising: a silicon substrate having a (111) surface; and NMOS and PMOS transistors formed on said (111) surface of said silicon substrate; wherein said PMOS and NMOS transistors have substantially matching switching characteristics and occupy substantially equal areas of said silicon substrate, and wherein gate oxides of said PMOS and NMOS transistors do not include any fluorine atoms.
Claim 6
Dependent Claim
62 words
An integrated circuit structure, comprising: a silicon substrate having a (111) surface; and NMOS and PMOS transistors formed on said (111) surface of said silicon substrate; wherein said PMOS and NMOS transistors have substantially matching switching characteristics and occupy substantially equal areas of said silicon substrate, and wherein gate oxides of said PMOS and NMOS transistors do not include any fluorine atoms.
Claim 7
Dependent Claim
30 words
An integrated circuit structure as in claim 4 , wherein at least one of each said NMOS and PMOS transistors are paired to form at least one CMOS transistor pair.
Claim 8
Independent Claim
43 words
A method of operating an integrated circuit comprising: providing an integrated circuit having PMOS and NMOS transistors fabricated in a (111) surface of a silicon substrate; and biasing said transistors to operate in a velocity saturation mode and with substantially matching switching characteristics.
Claim 9
Independent Claim
43 words
A method of operating an integrated circuit comprising: providing an integrated circuit having PMOS and NMOS transistors fabricated in a (111) surface of a silicon substrate; and biasing said transistors to operate in a velocity saturation mode and with substantially matching switching characteristics.
Claim 10
Dependent Claim
54 words
A memory circuit comprising: at least one pair of NMOS and PMOS transistors formed as a CMOS transistor pair on a (111) surface of a silicon substrate; wherein said PMOS and NMOS transistors are fabricated at less than 0.5 micron, have substantially matching switching characteristics and occupy substantially equal areas of said silicon substrate.
Claim 11
Dependent Claim
54 words
A memory circuit comprising: at least one pair of NMOS and PMOS transistors formed as a CMOS transistor pair on a (111) surface of a silicon substrate; wherein said PMOS and NMOS transistors are fabricated at less than 0.5 micron, have substantially matching switching characteristics and occupy substantially equal areas of said silicon substrate.
Claim 12
Dependent Claim
17 words
A memory circuit as in claim 7 , wherein said memory circuit is a DRAM memory circuit.
Claim 13
Dependent Claim
17 words
A memory circuit as in claim 7 , wherein said CMOS transistor pair forms a CMOS inverter.
Claim 14
Dependent Claim
80 words
A processor-based system comprising: a processor; a memory device coupled to said processor, said memory device comprising at least one memory circuit, said memory circuit comprising: a substrate having a (111) surface; and at least one pair of NMOS and PMOS transistors formed as a CMOS transistor pair fabricated on said (111) surface; wherein said PMOS and NMOS transistors are fabricated at less than 0.5 micron, have substantially matching switching characteristics and occupy substantially equal areas of said silicon substrate.
Claim 15
Dependent Claim
80 words
A processor-based system comprising: a processor; a memory device coupled to said processor, said memory device comprising at least one memory circuit, said memory circuit comprising: a substrate having a (111) surface; and at least one pair of NMOS and PMOS transistors formed as a CMOS transistor pair fabricated on said (111) surface; wherein said PMOS and NMOS transistors are fabricated at less than 0.5 micron, have substantially matching switching characteristics and occupy substantially equal areas of said silicon substrate.
Claim 16
Dependent Claim
15 words
A processor-based system as in claim 10 , wherein said memory device is a DRAM.
Claim 17
Dependent Claim
16 words
A processor-based system as in claim 10 , wherein said processor-based system is a computer system.
References Cited (Backward Citations)
US4857986A
Cited
US5227660A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-19 | 2006-02-18 | 2006-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-19 | 2010-02-18 | 2010-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-19 | 2014-02-18 | 2014-08-20 | $7700.00 | Window Closed / Lapsed |