US6431456B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
IC card
Assignee: NEC Electronics Corp
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Filing: 2001-03-19
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Granted: 2002-08-13
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Expires: 2021-03-19
Abstract
Abstract An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip ( 2 ) is mounted on a card substrate ( 1 ), and plural connection terminals ( 3 ) are exposed. The connection terminals are connected to predetermined external terminals ( 4 ) of the semiconductor integrated circuit chip, first overvoltage protection elements ( 7, 8, 9 ) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors ( 11 ) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements. The varistors have been selected by taking into consideration a relationship between the characteristics and the ability of the first overvoltage protection elements contained in the semiconductor integrated circuit chip, and exhibit the effect for preventing the electrostatic damage.
Inventors
- 👤 Hirotaka Nishizawa
- 👤 Yosuke Yukawa
- 👤 Takashi Totsuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:17
CPC Classifications
G; G06; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G06K19/077; G06K19/0772; G06K19/07735; G06K19/073; G06K19/07732; H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10W; H10W42/00; H10W42/60; H10W42/80; H10W70/00; H10W70/60; H10W70/611; H10W70/699; H10W90/00; H10W72/00; H10W72/071; H10W72/075; H10W72/50; H10W72/541; H10W72/547; H10W72/5473; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W72/951; H10W72/952; H10W74/00; H10W90/20; H10W90/24; H10W90/701; H10W90/731; H10W90/732; H10W90/734; H10W90/751; H10W90/752; H10W90/754; Y; Y10; Y10S; Y10S257/00; Y10S257/922
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
127 words
A method of recovering data from an IC card in which plural connection terminals are exposed, memory chips and a controller chip for controlling the memory chips are mounted on a card substrate, the connection terminals are connected to a first group of external terminals of the controller chip, the memory chips are connected to a second group of external terminals of the controller chip, and data evaluation terminals connected to the second group of external terminals are formed on the card substrate, the method including: a first processing for placing the memory chips in a state in which the memory chips cannot be controlled by the controller chip; and a second processing for reading the data from the data evaluation terminals by controlling the memory chips.
Claim 2
Independent Claim
127 words
A method of recovering data from an IC card in which plural connection terminals are exposed, memory chips and a controller chip for controlling the memory chips are mounted on a card substrate, the connection terminals are connected to a first group of external terminals of the controller chip, the memory chips are connected to a second group of external terminals of the controller chip, and data evaluation terminals connected to the second group of external terminals are formed on the card substrate, the method including: a first processing for placing the memory chips in a state in which the memory chips cannot be controlled by the controller chip; and a second processing for reading the data from the data evaluation terminals by controlling the memory chips.
Claim 3
Independent Claim
198 words
A method of recovering data from an IC card in which plural connection terminals are exposed, memory chips and a controller chip for controlling the memory chips are mounted on a card substrate, the controller chip having a privacy protection function that executes the encryption for the data that are written into the memory chips and the decryption for the data read out from the memory chips, and wherein the connection terminals are connected to a first group of external terminals of the controller chip, the memory chips are connected to a second group of external terminals of the controller chip, and data evaluation terminals connected to the second group of external terminals are formed on the card substrate, the method including: a first processing for controlling the output terminal included in the second group of external terminals of the controller chip so as to assume a state of high output impedance; a second processing for reading the data from the data evaluation terminals by controlling the memory; a third processing for decrypting the data read out in the second processing; and a fourth processing for writing the data decrypted in the third processing into another IC card.
Claim 4
Independent Claim
198 words
A method of recovering data from an IC card in which plural connection terminals are exposed, memory chips and a controller chip for controlling the memory chips are mounted on a card substrate, the controller chip having a privacy protection function that executes the encryption for the data that are written into the memory chips and the decryption for the data read out from the memory chips, and wherein the connection terminals are connected to a first group of external terminals of the controller chip, the memory chips are connected to a second group of external terminals of the controller chip, and data evaluation terminals connected to the second group of external terminals are formed on the card substrate, the method including: a first processing for controlling the output terminal included in the second group of external terminals of the controller chip so as to assume a state of high output impedance; a second processing for reading the data from the data evaluation terminals by controlling the memory; a third processing for decrypting the data read out in the second processing; and a fourth processing for writing the data decrypted in the third processing into another IC card.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-12 | 2006-02-11 | 2006-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-12 | 2010-02-11 | 2010-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-12 | 2014-02-11 | 2014-08-13 | $7700.00 | Window Closed / Lapsed |