Transparent continuous refresh RAM cell architecture

Claim 2

A memory block comprising: a memory cell array having a plurality of memory cells organized into rows and columns, each of the plurality of memory cells in a column is coupled to a read bit line and a write bit line; a plurality of sense amplifiers, each of the plurality of sense amplifiers being coupled to a corresponding read bit line; a plurality of write amplifiers, each of the plurality of write amplifiers being coupled to a corresponding write bit line; an access address buffer used to store an access address; and a refresh address generator for generating a refresh address, which is used to refresh the plurality of memory cells in the memory cell array, wherein a refresh operation using the refresh address and a write operation using the access address are performed substantially simultaneously, wherein each of the plurality of memory cells on each row is coupled to a read select line and a write select line, wherein a first row and a column of the plurality of memory cells is addressed by the refresh address for a read operation, and an associated one of the plurality of sense amplifiers is used to read from a first one of the plurality of memory cells, wherein a second row and the same column of the plurality of memory cells is addressed by the access address for the write operation, and an associated one of the plurality of write amplifiers is used to write to a second one of the plurality of memory cells, and wherein the first one of the plurality of memory cells is on the first row and the second one of the plurality of memory cells is on the second row, the first and second ones of the plurality of memory cells are on the same column, and the read operation and the write operation are performed substantially simultaneously.

Claim 3

The memory block of claim 1 wherein each of the plurality of memory cells is comprised of three transistors.

Claim 4

The memory block of claim 1 further comprising: an X decoder for decoding the access address and the refresh address to generate a read select signal on the read select line and a write select signal on the write select line; and a Y decoder for decoding the access address and the refresh address to generate a read bit line select signal to select one of the plurality of sense amplifiers for reading from the corresponding read bit line and a write bit line select signal to select one of the plurality of write amplifiers for writing on the corresponding write bit line.

Claim 5

The memory block of claim 1 wherein the write operation and the refresh operation are performed using different addresses.

Claim 6

The memory block of claim 4 further comprising a comparator to compare the access address against the refresh address to determine if the access address is the same as the refresh address.

Claim 7

The memory block of claim 5 wherein the refresh address is updated using a pre-determined algorithm if the access address is the same as the refresh address.

Claim 8

The memory block of claim 6 wherein the pre-determined algorithm includes incrementing the refresh address by one.

Claim 9

The memory block of claim 6 wherein the pre-determined algorithm includes decrementing the refresh address by one.

Claim 10

The memory block of claim 2 , wherein the three transistors comprise: a first transistor having a gate, a first terminal and a second terminal, the first terminal being coupled to the write bit line; a second transistor having a gate, a first terminal and a second terminal, the gate being coupled to the second terminal of the first transistor; and a third transistor having a gate, a first terminal and a second terminal, the first terminal being coupled to the read bit line and the second terminal being coupled to the first terminal of the second transistor.

Claim 11

The memory block of claim 9 , wherein the gate of the first transistor is coupled to the write select line.

Claim 12

The memory block of claim 10 , wherein the first terminal of the first transistor is coupled to the write amplifier over the write bit line.

Claim 13

The memory block of claim 11 , wherein the second terminal of the second transistor is coupled to ground.

Claim 14

The memory block of claim 12 , wherein the gate of the third transistor is coupled to the read select line.

Claim 15

The memory block of claim 13 , wherein the first terminal of the third transistor is coupled to the sense amplifier over the read bit line.

Claim 16

The memory block of claim 9 , wherein the first transistor, the second transistor and the third transistor are n-type transistors.

Claim 17

The memory block of claim 9 , wherein at least one of the first transistor, the second transistor and the third transistor is a p-type transistor.

Claim 18

A memory block comprising: a memory cell array having a plurality of memory cells organized into rows and columns, each of the plurality of memory cells in a column is coupled to a read bit line and a write bit line; a plurality of sense amplifiers, each of the plurality of sense amplifiers being coupled to a corresponding read bit line; a plurality of write amplifiers, each of the plurality of write amplifiers being coupled to a corresponding write bit line; an access address buffer used to store an access address; and a refresh address generator for generating a refresh address, which is used to refresh the plurality of memory cells in the memory cell array, wherein a refresh operation using the refresh address and a read operation using the access address are performed substantially simultaneously, wherein each of the plurality of memory cells on each row is coupled to a read select line and a write select line, wherein a first row and a column of the plurality of memory cells is addressed by the access address for the read operation, and an associated one of the plurality of sense amplifiers is used to read from a first one of the plurality of memory cells, wherein a second row and the same column of the plurality of memory cells is addressed by the refresh address for the write operation, and an associated one of the plurality of write amplifiers is used to write to a second one of the plurality of memory cells, and wherein the first one of the plurality of memory cells is on the first row and the second one of the plurality of memory cells is on the second row, the first and second ones of the plurality of memory cells are on the same column, and the read operation and the write operation are performed substantially simultaneously.

Claim 19

A memory block comprising: a memory cell array having a plurality of memory cells organized into rows and columns, each of the plurality of memory cells in a column is coupled to a read bit line and a write bit line; a plurality of sense amplifiers, each of the plurality of sense amplifiers being coupled to a corresponding read bit line; a plurality of write amplifiers, each of the plurality of write amplifiers being coupled to a corresponding write bit line; an access address buffer used to store an access address; and a refresh address generator for generating a refresh address, which is used to refresh the plurality of memory cells in the memory cell array, wherein a refresh operation using the refresh address and a read operation using the access address are performed substantially simultaneously, wherein each of the plurality of memory cells on each row is coupled to a read select line and a write select line, wherein a first row and a column of the plurality of memory cells is addressed by the access address for the read operation, and an associated one of the plurality of sense amplifiers is used to read from a first one of the plurality of memory cells, wherein a second row and the same column of the plurality of memory cells is addressed by the refresh address for the write operation, and an associated one of the plurality of write amplifiers is used to write to a second one of the plurality of memory cells, and wherein the first one of the plurality of memory cells is on the first row and the second one of the plurality of memory cells is on the second row, the first and second ones of the plurality of memory cells are on the same column, and the read operation and the write operation are performed substantially simultaneously.

Claim 22

The system-on-chip device of claim 18 further comprising a comparator to compare the refresh address to the write address, wherein the refresh address is updated if the refresh address is identical to the write address.

Claim 23

A memory chip comprising: a memory block including a memory cell array having a plurality of memory cells to store information, and a refresh address generator to generate a refresh address, which is used to refresh the plurality of memory cells; and an access address buffer used to store a write address, the write address being used during a write operation to write data into the memory cells, wherein the plurality of memory cells are organized into rows and columns and each of the plurality of memory cells in a column is coupled to a read bit line and a write bit line, and wherein a refresh operation using the refresh address and the write operation using the write address are performed substantially simultaneously, wherein a first row and a column of the plurality of memory cells is addressed by the refresh address for a read operation, and an associated one of the plurality of sense amplifiers is used to read from a first one of the plurality of memory cells, wherein a second row and the same column of the plurality of memory cells is addressed by the write address for the write operation, and an associated one of the plurality of write amplifiers is used to write to a second one of the plurality of memory cells, and wherein the first one of the plurality of memory cells is on the first row and the second one of the plurality of memory cells is on the second row, the first and second ones of the plurality of memory cells are on the same column, and the read operation and the write operation are performed substantially simultaneously.

Claim 24

A memory chip comprising: a memory block including a memory cell array having a plurality of memory cells to store information, and a refresh address generator to generate a refresh address, which is used to refresh the plurality of memory cells; and an access address buffer used to store a write address, the write address being used during a write operation to write data into the memory cells, wherein the plurality of memory cells are organized into rows and columns and each of the plurality of memory cells in a column is coupled to a read bit line and a write bit line, and wherein a refresh operation using the refresh address and the write operation using the write address are performed substantially simultaneously, wherein a first row and a column of the plurality of memory cells is addressed by the refresh address for a read operation, and an associated one of the plurality of sense amplifiers is used to read from a first one of the plurality of memory cells, wherein a second row and the same column of the plurality of memory cells is addressed by the write address for the write operation, and an associated one of the plurality of write amplifiers is used to write to a second one of the plurality of memory cells, and wherein the first one of the plurality of memory cells is on the first row and the second one of the plurality of memory cells is on the second row, the first and second ones of the plurality of memory cells are on the same column, and the read operation and the write operation are performed substantially simultaneously.

Claim 25

The memory chip of claim 20 further comprising a comparator to compare the refresh address to the write address, wherein the refresh address is updated if the refresh address is identical to the write address.

Claim 26

In a memory block having a plurality of memory cells organized into rows and columns, a method of refreshing a first memory cell while performing a write operation on a second memory cell, the method comprising the steps of: providing a write address to be used for the write operation; generating a refresh address to be used for a refresh operation; comparing the write address and the refresh address; updating the refresh address using a pre-determined algorithm if the write address and the refresh address are the same; and refreshing the first memory cell using the refresh address while substantially simultaneously performing the write operation on the second memory cell using the write address, wherein the first memory cell and the second memory cell are on different rows of the same column.

Claim 27

In a memory block having a plurality of memory cells organized into rows and columns, a method of refreshing a first memory cell while performing a write operation on a second memory cell, the method comprising the steps of: providing a write address to be used for the write operation; generating a refresh address to be used for a refresh operation; comparing the write address and the refresh address; updating the refresh address using a pre-determined algorithm if the write address and the refresh address are the same; and refreshing the first memory cell using the refresh address while substantially simultaneously performing the write operation on the second memory cell using the write address, wherein the first memory cell and the second memory cell are on different rows of the same column.

Claim 28

The method of refreshing a first memory cell of claim 22 wherein updating the refresh address includes incrementing the refresh address by one.

Claim 29

The method of refreshing of claim 22 wherein updating the refresh address includes decrementing the refresh address by one.

Claim 30

The method of refreshing of claim 22 , wherein the step of refreshing the first memory cell comprises the steps of: reading a data bit from the first memory cell and writing the data bit back to the first memory cell.