Method and apparatus for controlling both active and standby power in domino circuits

Claim 1

Apparatus for controlling both active and standby power in a domino circuit comprising: a precharge device connected to an intermediate precharge node; an input transistor network receiving a plurality of data inputs connected to said intermediate precharge node; an output inverter connected to said intermediate precharge node; said output inverter including a pair of transistors; a predefined transistor of said pair of transistors being arranged to minimize leakage current through said output inverter; a standby control signal; said standby control signal being asserted for a standby mode of the domino circuit and being unasserted for an active mode of the domino circuit; a clock input; a gate for combining said standby control signal and said clock signal to provide a combined standby clock signal; said combined standby clock signal for controlling said precharge device; said precharge device being deactivated responsive to said standby control signal being asserted; said precharge device being arranged to minimize leakage current through said deactivated precharge device; and a standby discharge device connected to said intermediate precharge node and controlled by said standby control signal; said standby discharge device being activated to discharge said intermediate precharge node responsive to said standby control signal being asserted.

Claim 19

A method for controlling both active and standby power in domino circuits including a precharge device coupled to an intermediate precharge node; an input transistor network receiving a plurality of data inputs connected to said intermediate precharge node; and an output inverter connected to said intermediate precharge node; the output inverter including a P-channel field effect transistor (PFET) and a N-channel field effect transistor (NFET); the PFET and the NFET of the output inverter having a gate connected to the intermediate precharge node; said method comprising the steps of: implementing the precharge device with a P-channel field effect transistor (PFET) having a predefined high voltage threshold or a design channel length to minimize leakage current through precharge PFET when deactivated; implementing the NFET of the output inverter with an N-channel field effect transistor (NFET) having a predefined high voltage threshold or a design channel length to minimize leakage current through the output inverter; providing a standby control signal; said standby control signal being asserted for a standby mode of the domino logic gate circuit and being unasserted for an active mode of the domino logic gate circuit; combining said standby control signal and a clock signal to provide a combined standby clock signal; gating the precharge PFET with said combined standby clock signal; the precharge PFET being deactivated responsive to said standby control signal being asserted; connecting a standby discharge device between the intermediate precharge node and ground, and applying said standby control signal to said standby discharge device for discharging the intermediate precharge node responsive to said standby control signal being asserted.

Claim 20

A method for controlling both active and standby power in domino circuits including a precharge device coupled to an intermediate precharge node; an input transistor network receiving a plurality of data inputs connected to said intermediate precharge node; and an output inverter connected to said intermediate precharge node; the output inverter including a P-channel field effect transistor (PFET) and a N-channel field effect transistor (NFET); the PFET and the NFET of the output inverter having a gate connected to the intermediate precharge node; said method comprising the steps of: implementing the precharge device with a P-channel field effect transistor (PFET) having a predefined high voltage threshold or a design channel length to minimize leakage current through precharge PFET when deactivated; implementing the NFET of the output inverter with an N-channel field effect transistor (NFET) having a predefined high voltage threshold or a design channel length to minimize leakage current through the output inverter; providing a standby control signal; said standby control signal being asserted for a standby mode of the domino logic gate circuit and being unasserted for an active mode of the domino logic gate circuit; combining said standby control signal and a clock signal to provide a combined standby clock signal; gating the precharge PFET with said combined standby clock signal; the precharge PFET being deactivated responsive to said standby control signal being asserted; connecting a standby discharge device between the intermediate precharge node and ground, and applying said standby control signal to said standby discharge device for discharging the intermediate precharge node responsive to said standby control signal being asserted.