Removable spacer technology using ion implantation to augment etch rate differences of spacer materials

Claim 1

A method of manufacturing a semiconductor device, which method comprises the steps of: (a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a surface of said substrate, said layer stack comprising: i. a thin gate insulating layer in contact with said substrate surface; and ii. a gate electrode layer formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface; (b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of said pair of opposing side surfaces, said first sidewall spacers comprising a first dielectric material; (c) forming a second, relatively wider, insulative, tapered sidewall spacer on each of said first sidewall spacers, said second sidewall spacers comprising a second dielectric material having an as-deposited etch resistance, said first and second dielectric materials of said first and second sidewall spacers being the same or different; (d) treating the second sidewall spacers to reduce the etch resistance of said second dielectric material from its as-deposited state to a more readily-etched state; (e) introducing dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent said first and second sidewall spacers to form a pair of spaced-apart, heavily-doped regions in said substrate; (f) etching to selectively remove the second sidewall spacers; (g) treating said pair of space-apart, heavily-doped regions to form a pair of heavily-doped source/drain regions in said substrate each having a junction therewith at a predetermined depth below said substrate surface, each of said heavily-doped source/drain regions being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the combined width of the lower ends of said first and second sidewall spacers adjacent said substrate surface; (h) introducing second, opposite conductivity type dopant impurities into exposed portions of said substrate surface intermediate said gate insulating layer or said first sidewall spacer and said heavily-doped source/drain regions to form lightly-or moderately-doped extension regions; and (i) treating said lightly- or moderately-doped extension regions to form a pair of shallow-depth, lightly- or moderately-doped source/drain extensions in said substrate, each of said shallow-depth, lightly-doped source/drain extensions extending from a proximal edge of a respective heavily-doped source/drain region to just beneath a respective proximal edge of said gate insulating layer, wherein step (a) comprises providing a silicon wafer substrate of n or p first conductivity type, said thin gate insulating layer comprises a silicon oxide layer about 25-50 Å thick, and said gate electrode layer comprises heavily-doped polysilicon.

Claim 2

A method of manufacturing a semiconductor device, which method comprises the steps of: (a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a surface of said substrate, said layer stack comprising: i. a thin gate insulating layer in contact with said substrate surface; and ii. a gate electrode layer formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface; (b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of said pair of opposing side surfaces, said first sidewall spacers comprising a first dielectric material; (c) forming a second, relatively wider, insulative, tapered sidewall spacer on each of said first sidewall spacers, said second sidewall spacers comprising a second dielectric material having an as-deposited etch resistance, said first and second dielectric materials of said first and second sidewall spacers being the same or different; (d) treating the second sidewall spacers to reduce the etch resistance of said second dielectric material from its as-deposited state to a more readily-etched state; (e) introducing dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent said first and second sidewall spacers to form a pair of spaced-apart, heavily-doped regions in said substrate; (f) etching to selectively remove the second sidewall spacers; (g) treating said pair of space-apart, heavily-doped regions to form a pair of heavily-doped source/drain regions in said substrate each having a junction therewith at a predetermined depth below said substrate surface, each of said heavily-doped source/drain regions being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the combined width of the lower ends of said first and second sidewall spacers adjacent said substrate surface; (h) introducing second, opposite conductivity type dopant impurities into exposed portions of said substrate surface intermediate said gate insulating layer or said first sidewall spacer and said heavily-doped source/drain regions to form lightly-or moderately-doped extension regions; and (i) treating said lightly- or moderately-doped extension regions to form a pair of shallow-depth, lightly- or moderately-doped source/drain extensions in said substrate, each of said shallow-depth, lightly-doped source/drain extensions extending from a proximal edge of a respective heavily-doped source/drain region to just beneath a respective proximal edge of said gate insulating layer, wherein step (a) comprises providing a silicon wafer substrate of n or p first conductivity type, said thin gate insulating layer comprises a silicon oxide layer about 25-50 Å thick, and said gate electrode layer comprises heavily-doped polysilicon.

Claim 17

A method of manufacturing a silicon-based MOS-type transistor, which method comprises the steps of: (a) providing a MOS transistor precursor structure comprising a silicon semiconductor wafer substrate of a first conductivity type and a layer stack formed on a portion of a surface of said wafer, said layer stack comprising: i. a thin gate insulating layer comprising a silicon oxide layer about 25-50 Å thick in contact with said wafer surface; and ii. a gate electrode layer comprising heavily-doped polysilicon formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface; (b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of said pair of opposing side surfaces, said first sidewall spacers comprising a dielectric material selected from silicon oxides, silicon nitrides, and silicon oxynitrides; (c) forming a second, relatively wider, insulative, tapered sidewall spacer on each of said first sidewall spacers, said second sidewall spacers comprising a UV-nitride dielectric material having an as-deposited etch resistance; (d) implanting said second sidewall spacers with impurities to reduce the etch resistance from its as-deposited state to a more readily-etched state; (e) implanting dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent said first and second sidewall spacers to form a pair of spaced-apart, heavily-doped implants in said wafer; (f) etching with dilute aqueous HF to selectively remove the second pair of sidewall spacers; (g) rapid thermal annealing to diffuse and activate the dopant impurities implanted in step (e), thereby forming a pair of heavily-doped source/drain regions in said wafer substrate, each having a junction therewith at a predetermined depth below said wafer surface, and being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the combined width of the lower ends of said first and second sidewall spacers adjacent said wafer surface; (h) implanting second, opposite conductivity type dopant impurities into exposed portions of said wafer surface intermediate said gate insulating layer or said first sidewall spacer and said heavily-doped source/drain regions to form lightly- or moderately-doped extension regions; and (i) rapid thermal annealing to diffuse and activate the dopant impurities implanted in step (h), thereby forming a pair of shallow-depth, lightly- or moderately-doped source/drain extensions extending from a proximal edge of a respective source/drain region to just beneath a respective proximal edge of said gate insulating layer.

Claim 18

A method of manufacturing a silicon-based MOS-type transistor, which method comprises the steps of: (a) providing a MOS transistor precursor structure comprising a silicon semiconductor wafer substrate of a first conductivity type and a layer stack formed on a portion of a surface of said wafer, said layer stack comprising: i. a thin gate insulating layer comprising a silicon oxide layer about 25-50 Å thick in contact with said wafer surface; and ii. a gate electrode layer comprising heavily-doped polysilicon formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface; (b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of said pair of opposing side surfaces, said first sidewall spacers comprising a dielectric material selected from silicon oxides, silicon nitrides, and silicon oxynitrides; (c) forming a second, relatively wider, insulative, tapered sidewall spacer on each of said first sidewall spacers, said second sidewall spacers comprising a UV-nitride dielectric material having an as-deposited etch resistance; (d) implanting said second sidewall spacers with impurities to reduce the etch resistance from its as-deposited state to a more readily-etched state; (e) implanting dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent said first and second sidewall spacers to form a pair of spaced-apart, heavily-doped implants in said wafer; (f) etching with dilute aqueous HF to selectively remove the second pair of sidewall spacers; (g) rapid thermal annealing to diffuse and activate the dopant impurities implanted in step (e), thereby forming a pair of heavily-doped source/drain regions in said wafer substrate, each having a junction therewith at a predetermined depth below said wafer surface, and being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the combined width of the lower ends of said first and second sidewall spacers adjacent said wafer surface; (h) implanting second, opposite conductivity type dopant impurities into exposed portions of said wafer surface intermediate said gate insulating layer or said first sidewall spacer and said heavily-doped source/drain regions to form lightly- or moderately-doped extension regions; and (i) rapid thermal annealing to diffuse and activate the dopant impurities implanted in step (h), thereby forming a pair of shallow-depth, lightly- or moderately-doped source/drain extensions extending from a proximal edge of a respective source/drain region to just beneath a respective proximal edge of said gate insulating layer.

Claim 21

A method of manufacturing a semiconductor device, which method comprises the steps of: (a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a surface of said substrate, said layer stack comprising: i. a thin gate insulating layer in contact with said substrate surface; and ii. a gate electrode layer formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface; (b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of said pair of opposing side surfaces, said first sidewall spacers comprising a first dielectric material; (c) forming a second relatively wider, insulative tapered sidewall spacer on each of said first sidewall spacers, said second sidewall spacers comprising a second dielectric material having an as-deposited etch resistance, said first and second dielectric materials of said first and second sidewall spacers being the same; (d) treating the second sidewall spacers to reduce the etch resistance of said second dielectric material from its as-deposited state to a more readily-etched state; (e) introducing dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent said first and second sidewall spacers to form a pair of spaced-apart, heavily-doped regions in said substrate; (f) etching to selectively remove the second sidewall spacers; (g) treating said pair of spaced-apart, heavily-doped regions to form a pair of heavily-doped source/drain regions in said substrate each having a junction therewith at a predetermined depth below said substrate surface, each of said heavily-doped source/drain regions being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the combined width of the lower ends of said first and second sidewall spacers adjacent said substrate surface; (h) introducing second, opposite conductivity type dopant impurities into exposed portions of said substrate surface intermediate said gate insulating layer or said first sidewall spacer and said heavily-doped source/drain regions to form lightly-or moderately-doped extension regions; and (i) treating and lightly- or moderately-doped extension regions to form a pair of shallow depth, lightly- or moderately-doped source/drain extension in said substrate, each of shallow-depth, lightly-doped source/drain extensions extending from a proximal edge of a respective heavily-doped source/drain region to just beneath a respective proximal edge of said gate insulating layer.

Claim 22

A method of manufacturing a semiconductor device, which method comprises the steps of: (a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a surface of said substrate, said layer stack comprising: i. a thin gate insulating layer in contact with said substrate surface; and ii. a gate electrode layer formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface; (b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of said pair of opposing side surfaces, said first sidewall spacers comprising a first dielectric material; (c) forming a second relatively wider, insulative tapered sidewall spacer on each of said first sidewall spacers, said second sidewall spacers comprising a second dielectric material having an as-deposited etch resistance, said first and second dielectric materials of said first and second sidewall spacers being the same; (d) treating the second sidewall spacers to reduce the etch resistance of said second dielectric material from its as-deposited state to a more readily-etched state; (e) introducing dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent said first and second sidewall spacers to form a pair of spaced-apart, heavily-doped regions in said substrate; (f) etching to selectively remove the second sidewall spacers; (g) treating said pair of spaced-apart, heavily-doped regions to form a pair of heavily-doped source/drain regions in said substrate each having a junction therewith at a predetermined depth below said substrate surface, each of said heavily-doped source/drain regions being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the combined width of the lower ends of said first and second sidewall spacers adjacent said substrate surface; (h) introducing second, opposite conductivity type dopant impurities into exposed portions of said substrate surface intermediate said gate insulating layer or said first sidewall spacer and said heavily-doped source/drain regions to form lightly-or moderately-doped extension regions; and (i) treating and lightly- or moderately-doped extension regions to form a pair of shallow depth, lightly- or moderately-doped source/drain extension in said substrate, each of shallow-depth, lightly-doped source/drain extensions extending from a proximal edge of a respective heavily-doped source/drain region to just beneath a respective proximal edge of said gate insulating layer.

Claim 29

A method of manufacturing a semiconductor device, which method comprises the steps of: (a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a substrate of said substrate, said layer stack comprising: i. a thin gate insulating layer in contact with said substrate surface; and ii. a gate electrode layer formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface; (b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of said pair of opposing side surfaces, said first sidewall spacers comprising a first dielectric material; (c) forming a second, relatively wider, insulative, tapered sidewall spacer on each of said fist sidewall spacers, said second sidewall spacers comprising a second dielectric material having an as-deposited etch resistance, said first and second dielectric materials of said first and second sidewall spacers being the same or different; (d) treating the second sidewall spacers to reduce the etch resistance of said second dielectric material from its as-deposited state to a more readily-etched state; (e) introducing dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent the first and second sidewall spacers to form a pair of spaced-apart, heavily-doped regions in said substrate; (f) etching to selectively remove the second sidewall spacers; (g) treating said pair of spaced-apart, heavily-doped regions to form a pair of heavily-doped source/drain regions in said substrate each having a junction therewith at a predetermined depth below said substrate surface, each of said heavily-doped source/drain regions being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the combined width of the lower ends of said first and second sidewall spacers adjacent said substrate surface; (h) introducing second, opposite conductivity type dopant impurities into exposed portions of said substrate surface intermediate said gate insulating layer or said first sidewall spacer and said heavily-doped source/drain regions to form lightly- or moderately-doped extension regions; and (i) treating said lightly- or moderately-doped extension regions to form a pair of shallow-depth, lightly- or moderately-doped source/drain extensions in said substrate, each of said shallow depth, lightly-doped source/drain extensions extending from a proximal edge of a respective heavily-doped source/drain region to just beneath a respective proximal edge of said gate insulating layer; wherein steps (d) and (e) are conducted separately.

Claim 30

A method of manufacturing a semiconductor device, which method comprises the steps of: (a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a substrate of said substrate, said layer stack comprising: i. a thin gate insulating layer in contact with said substrate surface; and ii. a gate electrode layer formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface; (b) forming a first, relatively narrow, insulative, tapered sidewall spacer on each of said pair of opposing side surfaces, said first sidewall spacers comprising a first dielectric material; (c) forming a second, relatively wider, insulative, tapered sidewall spacer on each of said fist sidewall spacers, said second sidewall spacers comprising a second dielectric material having an as-deposited etch resistance, said first and second dielectric materials of said first and second sidewall spacers being the same or different; (d) treating the second sidewall spacers to reduce the etch resistance of said second dielectric material from its as-deposited state to a more readily-etched state; (e) introducing dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent the first and second sidewall spacers to form a pair of spaced-apart, heavily-doped regions in said substrate; (f) etching to selectively remove the second sidewall spacers; (g) treating said pair of spaced-apart, heavily-doped regions to form a pair of heavily-doped source/drain regions in said substrate each having a junction therewith at a predetermined depth below said substrate surface, each of said heavily-doped source/drain regions being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the combined width of the lower ends of said first and second sidewall spacers adjacent said substrate surface; (h) introducing second, opposite conductivity type dopant impurities into exposed portions of said substrate surface intermediate said gate insulating layer or said first sidewall spacer and said heavily-doped source/drain regions to form lightly- or moderately-doped extension regions; and (i) treating said lightly- or moderately-doped extension regions to form a pair of shallow-depth, lightly- or moderately-doped source/drain extensions in said substrate, each of said shallow depth, lightly-doped source/drain extensions extending from a proximal edge of a respective heavily-doped source/drain region to just beneath a respective proximal edge of said gate insulating layer; wherein steps (d) and (e) are conducted separately.