US6420767B1
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Capacitively coupled DTMOS on SOI
Assignee: GlobalFoundries Inc
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Filing: 2000-06-28
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Granted: 2002-07-16
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Expires: 2020-06-28
Abstract
Abstract A transistor structure is provided comprising a source region having a N+ source region and a N- lightly doped source region. The structure also comprises a drain region having a N+ drain region and a N- lightly doped drain region. A P++ heavily doped region is provided. The P++ region resides alongside at least a portion of at least one of the N- lightly doped source region and N- lightly doped drain region. A P+ body region resides below a gate of the device and between the source and drain regions. The P+⇄ heavily doped region provides a capacitive coupling between a body region and the gate of the device and form a capacitive voltage divider with the junction capacitance of the device.
Inventors
- 👤 Srinath Krishnan
- 👤 John C. Holst
- 👤 Bin Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6708; H10D30/711
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
75 words
A MOSFET device, comprising: a lightly doped source extension region and a lightly doped drain extension region; and a heavily doped region, residing alongside at least a portion of one of the lightly doped source extension region and the lightly doped drain extension region, the heavily doped region providing a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the device between a body region and a gate region of the device.
Claim 2
Dependent Claim
75 words
A MOSFET device, comprising: a lightly doped source extension region and a lightly doped drain extension region; and a heavily doped region, residing alongside at least a portion of one of the lightly doped source extension region and the lightly doped drain extension region, the heavily doped region providing a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the device between a body region and a gate region of the device.
Claim 3
Dependent Claim
20 words
The device of claim 1 , the heavily doped region residing alongside at least a portion of a source region.
Claim 4
Dependent Claim
20 words
The device of claim 2 , the heavily doped region residing alongside at least a portion of a drain region.
Claim 5
Dependent Claim
25 words
The device of claim 1 , the lightly doped source extension region and the lightly doped drain extension region having a N − type implant.
Claim 6
Dependent Claim
28 words
The device of claim 4 , further comprising a source region and a drain region, the source region and the drain regions having a N + type implant.
Claim 7
Dependent Claim
16 words
The device of claim 5 , the heavily doped region having a P ++ type implant.
Claim 8
Dependent Claim
21 words
The device of claim 6 , the heavily doped region having a dopant concentration higher than the source and drain regions.
Claim 9
Dependent Claim
25 words
The device of claim 7 , the device having an SOI substrate and the heavily dopes region controlling the floating body effects in the device.
Claim 10
Dependent Claim
28 words
The device of claim 7 , the lightly doped source extension region, the lightly doped drain extension region and the heavily doped region residing under a gate structure.
Claim 11
Dependent Claim
127 words
A transistor device, comprising: a source region, comprising a N + source region and a N − lightly doped source region; a drain region, comprising a N + drain region and a N − lightly doped drain region; a P ++ heavily doped region, the P ++ heavily doped region residing alongside at least a portion of one of the N − lightly doped source region and the N − lightly doped drain region; and a P + body region residing below a gate of the device and between the source and drain regions; wherein the P ++ heavily doped region provides a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the device between the body region and the gate of the device.
Claim 12
Dependent Claim
127 words
A transistor device, comprising: a source region, comprising a N + source region and a N − lightly doped source region; a drain region, comprising a N + drain region and a N − lightly doped drain region; a P ++ heavily doped region, the P ++ heavily doped region residing alongside at least a portion of one of the N − lightly doped source region and the N − lightly doped drain region; and a P + body region residing below a gate of the device and between the source and drain regions; wherein the P ++ heavily doped region provides a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the device between the body region and the gate of the device.
Claim 13
Dependent Claim
20 words
The structure of claim 10 , the P ++ heavily doped region coupling the gate potential with the body potential.
Claim 14
Dependent Claim
23 words
The structure of claim 10 , the device having an SOI structure wherein the P + region facilitates control of floating body effects.
Claim 15
Dependent Claim
28 words
The structure of claim 10 , the P ++ heavily doped region having a dopant concentration higher than the N + source and the N + drain region.
Claim 16
Dependent Claim
26 words
The structure of claim 10 , the P ++ heavily doped region having a dopant concentration higher than a P + dopant concentration of the body.
Claim 17
Dependent Claim
28 words
The device of claim 11 , the N + drain and source regions having a dopant concentration higher than the N − lightly doped drain and source regions.
Claim 18
Dependent Claim
27 words
The device of claim 10 , the P ++ heavily doped region and the N − lightly doped drain and source regions residing below the gate structure.
Claim 19
Dependent Claim
106 words
An NMOS device, comprising: N + source and N + drain regions formed in a top silicon layer; and P ++ heavily doped region formed in the top silicon layer, the P ++ region having a higher dopant concentration than the N + source and N ++ drain regions, the P + region residing alongside at least a portion of at least one of the N − source and the N + drain regions; wherein the P ++ region provide a capacitive coupling between a body region and a gate of the device and form a capacitive voltage divider with the junction capacitance of the device.
Claim 20
Dependent Claim
106 words
An NMOS device, comprising: N + source and N + drain regions formed in a top silicon layer; and P ++ heavily doped region formed in the top silicon layer, the P ++ region having a higher dopant concentration than the N + source and N ++ drain regions, the P + region residing alongside at least a portion of at least one of the N − source and the N + drain regions; wherein the P ++ region provide a capacitive coupling between a body region and a gate of the device and form a capacitive voltage divider with the junction capacitance of the device.
Claim 21
Dependent Claim
27 words
The device of claim 16 , the P ++ heavily doped region and the N + source and N + drain regions residing below the gate structure.
Claim 22
Dependent Claim
64 words
A DTMOS device comprising: a source region; a drain region; a gate region; a body region; and a capacitive system formed from a heavily doped region and operatively coupled between the gate region and the drain region, the heavily doped region forming a capacitive voltage divider with the junction capacitance of the device between the body region and the gate region of the device.
Claim 23
Dependent Claim
64 words
A DTMOS device comprising: a source region; a drain region; a gate region; a body region; and a capacitive system formed from a heavily doped region and operatively coupled between the gate region and the drain region, the heavily doped region forming a capacitive voltage divider with the junction capacitance of the device between the body region and the gate region of the device.
Claim 24
Dependent Claim
38 words
The device of claim 19 , the source and drain regions formed by doping a substrate, the heavily doped region residing alongside at least a portion of at least one of the source region and the drain region.
Claim 25
Dependent Claim
21 words
The device of claim 20 , the heavily doped region and the source and drain regions residing below the gate region.
Claim 26
Independent Claim
84 words
A method of forming a MOSFET device, comprising the steps of: forming a lightly doped source extension region and a lightly doped drain extension region; and forming a heavily doped region, residing alongside at least a portion of one of the lightly doped source extension region and the lightly doped drain extension region, the heavily doped region providing a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the device between a body region and a gate region of the device.
Claim 27
Independent Claim
84 words
A method of forming a MOSFET device, comprising the steps of: forming a lightly doped source extension region and a lightly doped drain extension region; and forming a heavily doped region, residing alongside at least a portion of one of the lightly doped source extension region and the lightly doped drain extension region, the heavily doped region providing a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the device between a body region and a gate region of the device.
Claim 28
Dependent Claim
31 words
The method of claim 22 , further comprising the step of using the lightly doped source extension region and the lightly doped drain extension region having a N − type implant.
Claim 29
Dependent Claim
32 words
The method of claim 23 , further comprising the step of forming a source region and a drain region, the source region and the drain regions having a N + type implant.
Claim 30
Independent Claim
137 words
A method of forming a transistor, comprising the steps of: forming a source region, comprising a N + source region and a N − lightly doped source region; forming a drain region, comprising a N + drain region and a N − lightly doped drain region; forming a P ++ heavily doped region, the P ++ heavily doped region residing alongside at least a portion of one of the N − lightly doped source region and the N − lightly doped drain region; and forming a P + body region residing below a gate of the device and between the source and drain regions, wherein the P ++ heavily doped region provides a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the device between the body region and the gate of the device.
Claim 31
Independent Claim
137 words
A method of forming a transistor, comprising the steps of: forming a source region, comprising a N + source region and a N − lightly doped source region; forming a drain region, comprising a N + drain region and a N − lightly doped drain region; forming a P ++ heavily doped region, the P ++ heavily doped region residing alongside at least a portion of one of the N − lightly doped source region and the N − lightly doped drain region; and forming a P + body region residing below a gate of the device and between the source and drain regions, wherein the P ++ heavily doped region provides a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the device between the body region and the gate of the device.
Claim 32
Dependent Claim
81 words
The method of claim 25 , further comprising the step of using an arsenic dopant concentration of about 1×10 17 to 7×10 17 atoms/cm 3 at an implantation energy level within the range of 50 KeV to about 200 DeV in the source and drain regions, and a boron dopant concentration of about 1×10 18 to 1×10 19 atoms/cm 3 at an implantation enegry level with the range of about 1 KeV to about 100 KeV in the heavily doped region.
Claim 33
Dependent Claim
30 words
The method of claim 25 , further comprising the step of forming the P++ heavily doped region having a dopant concentration higher than a P++ dopant concentration of the body.
Claim 34
Dependent Claim
78 words
The device of claim 10 , the structure having an arsenic dopant concentration of about 1×10 17 to 7×10 17 atoms/cm 3 at an implantation energy level within the range of 50 KeV to about 200 KeV in the source and drain regions, and a boron dopant concentration of about 1×10 18 to 1× 19 atoms/cm 3 at an implantation energy level within the range of about 1 KeV to about 100 KeV in the heavily doped region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-07-15 | 2006-01-14 | 2006-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-15 | 2010-01-14 | 2010-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-15 | 2014-01-14 | 2014-07-16 | $7700.00 | Window Closed / Lapsed |