Patent US6415422B1 successfully refreshed from Google Patents.
US6415422B1
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Method and system for performing capacitance estimations on an integrated circuit design routed by a global routing tool
Assignee: International Business Machines Corp
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Filing: 1999-09-17
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Granted: 2002-07-02
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Expires: 2019-09-17
Abstract
Abstract A method for performing capacitance estimations on an integrated circuit design routed by a global routing tool is disclosed. Routing areas and pin locations of a net within an integrated circuit design are initially obtained from a global routing tool. Common boundaries among the routing areas are then defined. Before the performance of a detailed routing step, congestion information furnished by the global routing tool is utilized to perform probabilistic capacitance calculations for an interconnect that can be routed within the routing areas via the defined common boundaries to connect the pin locations.
Inventors
- 👤 Sharad Mehrotra
- 👤 Parsotam Trikam Patel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:04
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/36; G06F30/367
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
115 words
A method for performing capacitance estimations on an integrated circuit design that is routed by utilizing a global routing tool, said method comprising the steps of: obtaining routing areas and pin locations of a net within an integrated circuit design from a global routing tool; defining common boundaries among said routing areas; and before performing detailed routing, performing probabilistic capacitance calculations on an interconnect that can be routed within said routing areas via said common boundaries to connect said pin locations, including a probability that a track adjacent to said interconnect on one side is occupied by another interconnect, wherein said probabilistic capacitance calculations are performed utilizing congestion information furnished by said global routing tool.
Claim 2
Independent Claim
115 words
A method for performing capacitance estimations on an integrated circuit design that is routed by utilizing a global routing tool, said method comprising the steps of: obtaining routing areas and pin locations of a net within an integrated circuit design from a global routing tool; defining common boundaries among said routing areas; and before performing detailed routing, performing probabilistic capacitance calculations on an interconnect that can be routed within said routing areas via said common boundaries to connect said pin locations, including a probability that a track adjacent to said interconnect on one side is occupied by another interconnect, wherein said probabilistic capacitance calculations are performed utilizing congestion information furnished by said global routing tool.
Claim 3
Dependent Claim
40 words
The method according to claim 1 , wherein said probability is calculated by (m−1)/(n−1), where n is a number of tracks available in a given tile and m is a number of wires need to be routed within said tile.
Claim 4
Dependent Claim
44 words
The method according to claim 1 , wherein said step of performing probabilistic capacitance calculations further includes a step of calculating a probability of said track adjacent to said interconnect is open but a track beyond said track adjacent to said interconnect is occupied.
Claim 5
Dependent Claim
41 words
The method according to claim 3 , wherein said probability is calculated by (m−1)(n−m)/(n−1) (n−2), where n is a number of tracks available in a given tile and m is a number of wires need to be routed within said tile.
Claim 6
Dependent Claim
37 words
The method according to claim 3 , wherein said step of performing probabilistic capacitance calculations further includes a step of calculating a probability of a next occupied track is more than two tracks away from said interconnect.
Claim 7
Dependent Claim
42 words
The method according to claim 5 , wherein said probability is calculated by 1−{[(m−1)/(n−1)]+[(m−1) (n−m)/(n−1) (n−2)]}, where n is a number of tracks available in a given tile and m is a number of wires need to be routed within said tile.
Claim 8
Dependent Claim
134 words
A computer program product residing on a computer usable medium for performing capacitance estimations on an integrated circuit design that is routed by utilizing a global routing tool, said computer program product comprising: program code means for obtaining routing areas and pin locations of a net within an integrated circuit design from a global routing tool; program code means for defining common boundaries among said routing areas; and program code means for performing probabilistic capacitance calculations on an interconnect that can be routed within said routing areas via said common boundaries to connect said pin locations, before performing detailed routing, including a probability that a track adjacent to said interconnect on one side is occupied by another interconnect, wherein said probabilistic capacitance calculations are performed utilizing congestion information furnished by said global routing tool.
Claim 9
Dependent Claim
134 words
A computer program product residing on a computer usable medium for performing capacitance estimations on an integrated circuit design that is routed by utilizing a global routing tool, said computer program product comprising: program code means for obtaining routing areas and pin locations of a net within an integrated circuit design from a global routing tool; program code means for defining common boundaries among said routing areas; and program code means for performing probabilistic capacitance calculations on an interconnect that can be routed within said routing areas via said common boundaries to connect said pin locations, before performing detailed routing, including a probability that a track adjacent to said interconnect on one side is occupied by another interconnect, wherein said probabilistic capacitance calculations are performed utilizing congestion information furnished by said global routing tool.
Claim 10
Dependent Claim
42 words
The computer program product according to claim 7 , wherein said probability is calculated by (m−1)/(n−1), where n is a number of tracks available in a given tile and m is a number of wires need to be routed within said tile.
Claim 11
Dependent Claim
50 words
The computer program product according to claim 7 , wherein said program code means for performing probabilistic capacitance calculations further includes a program code means for calculating a probability of said track adjacent to said interconnect is open but a track beyond said track adjacent to said interconnect is occupied.
Claim 12
Dependent Claim
42 words
The computer program product according to claim 9 , wherein said probability is calculated by (m−1)(n−m)/(n−1)(n−2), where n is a number of tracks available in a given tile and m is a number of wires need to be routed within said tile.
Claim 13
Dependent Claim
43 words
The computer program product according to claim 9 , wherein said program code means for performing probabilistic capacitance calculations further includes a program code means for calculating a probability of a next occupied track is more than two tracks away from said interconnect.
Claim 14
Dependent Claim
42 words
The computer program product according to claim 11 , wherein said probability is calculated by 1−{[(m−1)/(n−1)]+[(m−1)(n−m)/(n−1)(n−2)]}, where n is a number of tracks available in a given tile and m is a number of wires need to be routed within said tile.
Claim 15
Dependent Claim
120 words
A computer system for performing capacitance estimations on an integrated circuit design that is routed by utilizing a global routing tool, said computer system comprising: means for obtaining routing areas and pin locations of a net within an integrated circuit design from a global routing tool; means for defining common boundaries among said routing areas; and means for performing probabilistic capacitance calculations on an interconnect that can be routed within said routing areas via said common boundaries to connect said pin locations, before performing detailed routing, including a probability that a track adjacent to said interconnect on one side is occupied by another interconnect, wherein said probabilistic capacitance calculations are performed utilizing congestion information furnished by said global routing tool.
Claim 16
Dependent Claim
120 words
A computer system for performing capacitance estimations on an integrated circuit design that is routed by utilizing a global routing tool, said computer system comprising: means for obtaining routing areas and pin locations of a net within an integrated circuit design from a global routing tool; means for defining common boundaries among said routing areas; and means for performing probabilistic capacitance calculations on an interconnect that can be routed within said routing areas via said common boundaries to connect said pin locations, before performing detailed routing, including a probability that a track adjacent to said interconnect on one side is occupied by another interconnect, wherein said probabilistic capacitance calculations are performed utilizing congestion information furnished by said global routing tool.
Claim 17
Dependent Claim
41 words
The computer system according to claim 13 , wherein said probability is calculated by (m−1)/(n−1), where n is a number of tracks available in a given tile and m is a number of wires need to be routed within said tile.
Claim 18
Dependent Claim
45 words
The computer system according to claim 13 , wherein said means for performing probabilistic capacitance calculations further includes a means for calculating a probability of said track adjacent to said interconnect is open but a track beyond said track adjacent to said interconnect is occupied.
Claim 19
Dependent Claim
38 words
The computer system according to claim 15 , wherein said means for performing probabilistic capacitance calculations further includes a means for calculating a probability of a next occupied track is more than two tracks away from said interconnect.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-01 | 2005-12-31 | 2006-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-01 | 2009-12-31 | 2010-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-01 | 2013-12-31 | 2014-07-02 | $7700.00 | Window Closed / Lapsed |