Bus mastering interface control system for transferring multistream data over a host bus

Claim 2

A bus interface control system for transferring data over a host bus operatively coupled to at least one host processor wherein the host processor receives multistream data and stores the received multistream data in a fragmented buffer, comprising: first multistream processor for processing multistream data packets transferred over the host bus; and master interface mans, operatively coupled to the first multistream processor and the buffer, for independently requesting the multistream data from the fragmented buffer in variable data packet sizes that are independent of fragmented memory sizes without requesting host processor intervention between requests for data packets.

Claim 3

The bus interface control system of claim 1 including means for storing data representing fragmented memory locations and for storing a size of each memory fragment as part of stream description data for at least one stream of the multistream data; and means, responsive to the stream description data, for periodically programming stream configuration data based on the stream descriptor data in stream configuration data storage designated for each stream.

Claim 4

The bus interface control system of claim 1 wherein the master interface means for independently requesting the multistream data further includes: multistream data packet FIFO memory; and means, operatively coupled to the multistream data packet FIFO memory, for controlling the data packet FIFO memory to facilitate transfer of multistream data packets between the first multistream processor and the means for transferring.

Claim 5

The bus interface control system of claim 2 further including a second multistream processor for processing multistream data packets transferred over the host bus and wherein the master interface means further includes an arbitor operatively coupled to the first and second multistream processors for asynchronously arbitrating storage of data packets in a data packet FIFO memory, on a per data packet basis, between the first and second multistream processors.

Claim 6

The bus interface control system of claim 3 wherein the means for controlling the data packet FIFO includes a write request register containing at least data representing a number of bytes in a data packet stored in the data packet FIFO to independently transfer to the buffer, and data stream identification data identifying the multistream the bytes belong to.

Claim 7

The bus interface control system of claim 4 wherein the buffer is in host memory, the multistream data includes multiple streams of digital audio data and the first and second multistream processors are digital signal processors that request the multistream data from the buffer as variable length data packets on-demand without interrupting processing by the host processor between independent requests for data packets.

Claim 8

The bus interface control system of claim 5 wherein the means for controlling the data packet FIFO further includes a data packet FIFO read status register containing at least data representing a number of bytes in the data packet FIFO received from the buffer, and data representing an end of stream as received from the host processor.

Claim 9

The bus interface control system of claim 3 wherein the FIFO memory stores a data packet from each of the different streams on a packet by packet basis to facilitate multitasking by a digital signal processor (DSP) operatively coupled to the bus interface control system.

Claim 10

The bus interface control system of claim 1 wherein the master bus interface includes means for hopping among designated fragmented memory sections on a per stream basis to obtain stream data for each stream.

Claim 11

The bus interface control system of claim 1 wherein the master bus interface dynamically updates stream description data after each transfer.

Claim 12

The bus interface control system of claim 1 including bus master stream identification registers as a bank of registers for each stream.

Claim 13

A bus interface control system for transferring data over a host bus operatively coupled to at least one host processor that receives multistream data, for storing the received multistream data in a fragmented buffer, comprising: first multistream processor for processing multistream data packets transferred over the host bus; at least a second multistream processor for processing multistream data packets transferred over the host bus; and master interface means, operatively coupled to the first and second multistream processors and the buffer, for independently requesting the multistream data from the fragmented buffer in variable data packet sizes that are independent of fragmented memory sizes without requesting host processor intervention between requests for data packets wherein the master interface means further includes: an arbitor operatively coupled to the first and second multistream processors for arbitrating storage of data packets, on a per data packet basis, between the first and second multistream processors; multistream data packet FIFO memory, operatively coupled to the arbitor, for storing the data packets; and means, operatively coupled to the multistream data packet FIFO memory, for controlling the data packet FIFO to facilitate transfer of multistream data packets between the first and second multistream processors and the buffer.

Claim 14

A bus interface control system for transferring data over a host bus operatively coupled to at least one host processor that receives multistream data, for storing the received multistream data in a fragmented buffer, comprising: first multistream processor for processing multistream data packets transferred over the host bus; at least a second multistream processor for processing multistream data packets transferred over the host bus; and master interface means, operatively coupled to the first and second multistream processors and the buffer, for independently requesting the multistream data from the fragmented buffer in variable data packet sizes that are independent of fragmented memory sizes without requesting host processor intervention between requests for data packets wherein the master interface means further includes: an arbitor operatively coupled to the first and second multistream processors for arbitrating storage of data packets, on a per data packet basis, between the first and second multistream processors; multistream data packet FIFO memory, operatively coupled to the arbitor, for storing the data packets; and means, operatively coupled to the multistream data packet FIFO memory, for controlling the data packet FIFO to facilitate transfer of multistream data packets between the first and second multistream processors and the buffer.

Claim 15

The bus interface control system of claim 12 wherein the means for controlling the data packet FIFO includes a write request register containing at least data representing a number of bytes in a data packet stored in the data packet FIFO to independently transfer to the buffer, and data stream identification data identifying the multistream the bytes belong to.

Claim 16

The bus interface control system of claim 13 wherein the buffer is in host memory, the multistream data includes multiple streams of digital audio data and the first and second multistream processors are digital signal processors that request the multistream data from the buffer as variable length data packets on-demand without interrupting processing by the host processor between independent requests for data packets.

Claim 17

The bus interface control system of claim 14 wherein the means for controlling the data packet FIFO further includes a data packet FIFO read status register containing at least data representing a number of bytes in the data packet FIFO received from the buffer, and data representing an end of stream as received from the host processor.

Claim 20

The method of claim 16 including the step of processing, by a second multistream processor, multistream data packets transferred over the host bus and including the step of arbitrating storage of data packets using a data packet FIFO memory, on a per data packet basis, between the first and second multistream processors.

Claim 21

The method of claim 17 wherein the buffer is in host memory, the multistream data includes multiple streams of digital audio data and the first and second multistream processors are digital signal processors that request the multistream data from the buffer as variable length data packets on-demand without interrupting processing by the host processor between independent requests for data packets.