US6414355B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness
Assignee: Advanced Micro Devices Inc
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Filing: 2001-01-26
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Granted: 2002-07-02
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Expires: 2021-01-26
Abstract
Abstract A silicon-on-insulator (SOI) chip. The SOI chip has a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first and a second tile, the first tile having a first thickness and the second tile having a second thickness, the second thickness being smaller than the first thickness. Also disclosed is a method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile.
Inventors
- 👤 Judy Xilin An
- 👤 Bin Yu
- 👤 William G. En
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:52
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201; H10D86/01
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
79 words
A silicon-on-insulator (SOI) chip, comprising: a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first and a second tile, the first tile having a first thickness and a plurality of partially depleted semiconductor devices formed therefrom, and the second tile having a second thickness and a plurality of fully depleted devices formed therefrom, the second thickness being smaller than the first thickness.
Claim 2
Dependent Claim
79 words
A silicon-on-insulator (SOI) chip, comprising: a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first and a second tile, the first tile having a first thickness and a plurality of partially depleted semiconductor devices formed therefrom, and the second tile having a second thickness and a plurality of fully depleted devices formed therefrom, the second thickness being smaller than the first thickness.
Claim 3
Dependent Claim
24 words
The SOI chip according to claim 1 , wherein the partially depleted devices form digital circuitry and the fully depleted devices form analog circuitry.
Claim 4
Dependent Claim
20 words
The SOI chip according to claim 1 , wherein the first thickness is about 800 Å to about 1500 Å.
Claim 5
Dependent Claim
20 words
The SOI chip according to claim 1 , wherein the second thickness is about 500 Å to about 1000 Å.
Claim 6
Dependent Claim
35 words
The SOI chip according to claim 1 , wherein the active layer has an initially uniform thickness and the thickness of the active layer in the area of the second tile is reduced by etching.
Claim 7
Dependent Claim
36 words
The SOI chip according to claim 1 , wherein the active layer has an initially uniform thickness and the thickness of the active layer in the area of the first tile is increased by silicon deposition.
Claim 8
Dependent Claim
55 words
The SOI chip according to claim 1 , wherein the active layer has an initially uniform thickness and the thickness of the active layer in the area of the second tile is reduced by implanting oxygen to form a layer of silicon dioxide in a lower portion of the active layer adjacent the BOX layer.
Claim 9
Dependent Claim
33 words
The SOI chip according to claim 1 , wherein each partially depleted device has an active region that includes a source, a drain and a body disposed between the source and the drain.
Claim 10
Dependent Claim
27 words
The SOI chip according to claim 8 , wherein the active layer in the area of each body of the partially depleted devices has a uniform thickness.
Claim 11
Dependent Claim
38 words
The SOI chip according to claim 8 , wherein each fully depleted device has an active region that includes a source, a drain and a body disposed between the source and the drain of the fully depleted device.
Claim 12
Dependent Claim
27 words
The SOI chip according to claim 10 , wherein the active layer in the area of each body of the fully depleted devices has a uniform thickness.
Claim 13
Dependent Claim
56 words
The SOI chip according to claim 10 , wherein the active layer in the area of each body of the partially depleted devices has a uniform thickness proportional to the first thickness and the active layer in the area of each body of the fully depleted devices has a uniform thickness proportional to the second thickness.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-01 | 2005-12-31 | 2006-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-01 | 2009-12-31 | 2010-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-01 | 2013-12-31 | 2014-07-02 | $7700.00 | Window Closed / Lapsed |