MIS semiconductor device having body-contact region

Claim 2

A MIS semiconductor device using a semiconductor active layer stacked on an insulating layer, comprising: a pair of first regions of a first conductivity type arranged in said active layer; a second region of a second conductivity type arranged in said active layer and interposed between said pair of first regions; a third region of the second conductivity type arranged in said active layer adjacent to said second region; and a gate electrode having first and second portions facing said second and third regions, respectively, through a gate insulating film, in which a main MIS capacitor and a parasitic MIS capacitor are formed under said first and second portions of said gate electrode, respectively, wherein said second and third regions are arranged to have different impurity concentrations.

Claim 3

The device according to claim 1, wherein said third region is doped with an impurity under a condition different from that of the second region.

Claim 4

The device according to claim 2, wherein said condition for doping said third region with said impurity is arranged such that capacitance of said parasitic MIS capacitor becomes substantially smallest, in the operation voltage range of said device.

Claim 5

The device according to claim 3, further comprising a contact region having a resistivity lower than that of said second region and arranged in said active layer, to be connected to a wiring for applying an electric potential to said second region.

Claim 6

The device according to claim 4, wherein said condition for doping said third region with said impurity is arranged such that leakage current flowing between said first region and said contact region is reduced, in the operation voltage range of said device.

Claim 7

The device according to claim 5, wherein said main MIS capacitor is part of a MISFET in which said first regions are source and drain regions, and said second region is a channel region.

Claim 8

The device according to claim 1, further comprising a semiconductor support layer arranged to face said active layer through said insulating layer.

Claim 9

A MIS semiconductor device using a semiconductor active layer stacked on an insulating layer, comprising: a pair of first regions of a first conductivity type arranged in said active layer; a second region of a second conductivity type arranged in said active layer and interposed between said pair of first regions; a third region of the second conductivity type arranged in said active layer adjacent to said second region; and a gate electrode having first and second portions facing said second and third regions, respectively, through a gate insulating film, in which a main MIS capacitor and a parasitic MIS capacitor are formed under said first and second portions of said gate electrode, respectively, wherein said first and second portions of said gate electrode are arranged to have different work functions.

Claim 10

A MIS semiconductor device using a semiconductor active layer stacked on an insulating layer, comprising: a pair of first regions of a first conductivity type arranged in said active layer; a second region of a second conductivity type arranged in said active layer and interposed between said pair of first regions; a third region of the second conductivity type arranged in said active layer adjacent to said second region; and a gate electrode having first and second portions facing said second and third regions, respectively, through a gate insulating film, in which a main MIS capacitor and a parasitic MIS capacitor are formed under said first and second portions of said gate electrode, respectively, wherein said first and second portions of said gate electrode are arranged to have different work functions.

Claim 11

The device according to claim 8, wherein said work function of said second portion of said gate electrode is arranged such that capacitance of said parasitic MIS capacitor becomes substantially smallest, in the operation voltage range of said device.

Claim 12

The device according to claim 9, further comprising a contact region having a resistivity lower than that of said second region and arranged in said active layer, to be connected to a wiring for applying an electric potential to said second region.

Claim 13

The device according to claim 10, wherein said work function of said second portion of said gate electrode is arranged such that leakage current flowing between said first region and said contact region is reduced, in the operation voltage range of said device.

Claim 14

The device according to claim 11, wherein said first and second portions of said gate electrode comprise semiconductor layers having different conductivity types from each other, and a conductive layer is disposed on said gate electrode to electrically connect said first and second portions.

Claim 15

The device according to claim 11, wherein said first and second portions of said gate electrode consist essentially of metal materials having work functions different from each other.

Claim 16

The device according to claim 11, wherein said main MIS capacitor is part of a MISFET in which said first regions are source and drain regions, and said second region is a channel region.

Claim 17

The device according to claim 8, further comprising a semiconductor support layer arranged to face said active layer through said insulating layer.

Claim 18

A MIS semiconductor device using a semiconductor active layer stacked on an insulating layer, comprising: a pair of first regions of a first conductivity type arranged in said active layer; a second region of a second conductivity type arranged in said active layer and interposed between said pair of first regions; a third region of the second conductivity type arranged in said active layer adjacent to said second region; a gate electrode having first and second portions facing said second and third regions, respectively, through a gate insulating film, in which a main MIS capacitor and a parasitic MIS capacitor are formed under said first and second portions of said gate electrode, respectively; and setting means for decreasing electrical charges necessary for charging and discharging said parasitic MIS capacitor, in an operation voltage range of said device, wherein, in said main MIS capacitor and said parasitic MIS capacitor, said gate insulating film has a substantially uniform thickness, and said second and third regions have substantially the same thickness as each other.

Claim 19

A MIS semiconductor device using a semiconductor active layer stacked on an insulating layer, comprising: a pair of first regions of a first conductivity type arranged in said active layer; a second region of a second conductivity type arranged in said active layer and interposed between said pair of first regions; a third region of the second conductivity type arranged in said active layer adjacent to said second region; a gate electrode having first and second portions facing said second and third regions, respectively, through a gate insulating film, in which a main MIS capacitor and a parasitic MIS capacitor are formed under said first and second portions of said gate electrode, respectively; and setting means for decreasing electrical charges necessary for charging and discharging said parasitic MIS capacitor, in an operation voltage range of said device, wherein, in said main MIS capacitor and said parasitic MIS capacitor, said gate insulating film has a substantially uniform thickness, and said second and third regions have substantially the same thickness as each other.

Claim 20

The device according to claim 16, wherein it is set by said setting means such that capacitance of said parasitic MIS capacitor becomes substantially smallest, in the operation voltage range of said device.

Claim 21

The device according to claim 17, further comprising a contact region having a resistivity lower than that of said second region and arranged in said active layer, to be connected to a wiring for applying an electric potential to said second region.

Claim 22

The device according to claim 18, wherein it is set by said setting means such that leakage current flowing between said first region and said contact region is reduced, in the operation voltage range of said device.

Claim 23

The device according to claim 19, wherein said main MIS capacitor is part of a MISFET in which said first regions are source and drain regions, and said second region is a channel region.

Claim 24

The apparatus according to claim 1, wherein said second and third regions have different impurity concentrations such that electrical charges necessary for charging and discharging said parasitic MIS capacitor are decreased, in an operation voltage range of said device.

Claim 25

The apparatus according to claim 8, wherein said first and second portions of said gate electrode are arranged to have different work functions such that electrical charges necessary for charging and discharging said parasitic MIS capacitor are decreased, in an operation voltage range of said device.

Claim 26

The apparatus according to claim 1, wherein said third region has an impurity concentration higher than that of said second region.