US6404572B1
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Circuit and method for generating a write precompensation signal
Assignee: Texas Instruments Inc
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Filing: 1999-05-05
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Granted: 2002-06-11
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Expires: 2019-05-05
Abstract
Abstract A circuit that generates a write precompensation delay signal includes a precoder, a delayed clock pulse selector, a delayed clock pulse generator, and a non-return-to-zero (NRZ) modulator. A master clock signal and serialized data operating at the master clock rate are inputs to the precoder which generates a precoded data signal operating at the master clock rate. The delayed clock pulse selector generates clock pulse selection signals based on the precoded data. The delayed clock pulse generator generates at least two delayed clock signals, selects either none or one of the delayed clock signals according to the clock pulse selection signals, and generates a return-to-zero (RZ) signal whose time periods comprise either a zero if no delayed clock signal is selected or a pulse of the selected delayed clock signal. The NRZ modulator generates the precompensation signal from the RZ signal, and the precompensation signal has a maximum precompensation delay of at least 50% of the master clock time period. Preferably, the precompensation circuit also includes a ramp waveform and threshold voltage generator to generate at least one ramp waveform and at least two threshold voltages. A preferred embodiment of the invention includes time-interleaving the precoded data into odd and even data sequences each operating at half the master clock rate. In this case, the ramp waveform and threshold voltage generator preferably generates an odd and an even waveform.
Inventors
- 👤 Ghy-Boong Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:22
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; G11B20/10009; G11B5/00; G11B5/012; G11B5/02; G11B5/09
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
143 words
A circuit for generating a write precompensation signal having precompensation delay, said circuit comprising: a precoder for precoding serialized input data to generate a precoded data signal operating at a master clock rate; a delayed clock pulse selector for generating clock pulse selection signals based on said precoded data; a delayed clock pulse generator for generating at least two delayed clock signals, for selecting either none or one of said delayed clock signals according to said clock pulse selection signals, and for generating a return-to-zero (RZ) signal whose time periods comprise either a zero if no delayed clock signal is selected or a pulse of said selected delayed clock signal; and a non-return-to-zero (NRZ) modulator for generating said precompensation signal from said RZ signal, wherein the maximum precompensation delay of said precompensation signal is at least 50% of the master clock time period.
Claim 2
Dependent Claim
143 words
A circuit for generating a write precompensation signal having precompensation delay, said circuit comprising: a precoder for precoding serialized input data to generate a precoded data signal operating at a master clock rate; a delayed clock pulse selector for generating clock pulse selection signals based on said precoded data; a delayed clock pulse generator for generating at least two delayed clock signals, for selecting either none or one of said delayed clock signals according to said clock pulse selection signals, and for generating a return-to-zero (RZ) signal whose time periods comprise either a zero if no delayed clock signal is selected or a pulse of said selected delayed clock signal; and a non-return-to-zero (NRZ) modulator for generating said precompensation signal from said RZ signal, wherein the maximum precompensation delay of said precompensation signal is at least 50% of the master clock time period.
Claim 3
Dependent Claim
76 words
The circuit according to claim 1 , wherein said precoder comprises: a D-flip flop whose-clock input operates at said master clock rate; an XOR gate, having said serialized input data as a first input and having the output of said D-flip flop as a second input, wherein the output of said XOR gate is provided to the data input of said D-flip flop and wherein the output of said D-flip flop is the precoded data signal.
Claim 4
Dependent Claim
18 words
The circuit according to claim 1 , wherein said delayed clock pulse generator generates four delayed clock signals.
Claim 5
Dependent Claim
135 words
The circuit according to claim 3 , wherein if the current precoded data bit equals zero, said delayed clock pulse generator selects no delayed clock signal, and wherein if the current precoded data bit equals one, said delayed clock pulse generator selects one delayed clock signal based on the values of the previous two precoded data bits, wherein: a first delayed clock signal is selected when the previous two precoded data bits both equal zero; a second delayed clock signal is selected when the previous two precoded data bits equal a zero and a one, respectively; a third delayed clock signal is selected when the previous two precoded data bits equal a one and a zero, respectively; and a fourth delayed clock signal is selected when the previous two precoded data bits both equal one.
Claim 6
Dependent Claim
52 words
The circuit according to claim 1 , further comprising a ramp waveform and threshold voltage generator for generating at least one ramp waveform and at least two threshold voltages, wherein said delayed clock pulse generator compares said at least one ramp waveform to said threshold voltages to generate said delayed clock signals.
Claim 7
Dependent Claim
54 words
The circuit according to claim 5 , further comprising a current-proportional-to-frequency generator for generating a current proportional to said master clock rate and providing said current to said ramp waveform and threshold voltage generator, wherein the peak-to-peak voltage of said at least one ramp waveform is maintained constant regardless of said master clock rate.
Claim 8
Dependent Claim
103 words
The circuit according to claim 6 , further comprising: a time-interleaver for time-interleaving said precoded data signal into odd and even data sequences each operating at half said master clock rate, wherein: said clock pulse selection signals are based on said time-interleaved data sequences; said current to said delayed clock pulse generator generates at least two odd and two even delayed clock signals and generates an odd RZ signal and an even RZ signal, said odd and even RZ signals operating at half said master clock rate; and said NRZ modulator generates said RZ signal by combining said odd and even RZ signals.
Claim 9
Dependent Claim
21 words
The circuit according to claim 7 , wherein said ramp waveform and threshold voltage generator generates odd and even ramp waveforms.
Claim 10
Dependent Claim
87 words
The circuit according to claim 7 , wherein said time-interleaver comprises: a D-flip flop for generating an odd clock signal and an even clock signal each operating at half the master clock rate, the clock input of said D-flip flop operating at said master clock rate; a series of odd D-flip flops clocked by said odd clock signal; and a series of even D-flip flops clocked by said even clock signal, wherein said precoded data signal is provided to said odd and even series of D-flip flops.
Claim 11
Independent Claim
128 words
A method for generating a write precompensation signal having precompensation delay, said signal operating at a master clock rate, said method comprising the steps of: precoding serialized input data operating at said master clock rate; generating at least two delayed clock signals; selecting either none or one of said delayed clock signals based on said precoded data; generating a return-to-zero (RZ) signal operating at said master clock rate, each time period of said RZ signal comprising either a zero if no delayed clock signal is selected or a pulse of said selected delayed clock signal; and generating said precompensation signal as a non-return-to-zero (NRZ) version of said RZ signal, wherein the maximum precompensation delay of said precompensation signal is at least 50% of the master clock time period.
Claim 12
Independent Claim
128 words
A method for generating a write precompensation signal having precompensation delay, said signal operating at a master clock rate, said method comprising the steps of: precoding serialized input data operating at said master clock rate; generating at least two delayed clock signals; selecting either none or one of said delayed clock signals based on said precoded data; generating a return-to-zero (RZ) signal operating at said master clock rate, each time period of said RZ signal comprising either a zero if no delayed clock signal is selected or a pulse of said selected delayed clock signal; and generating said precompensation signal as a non-return-to-zero (NRZ) version of said RZ signal, wherein the maximum precompensation delay of said precompensation signal is at least 50% of the master clock time period.
Claim 13
Dependent Claim
82 words
The method according to claim 10 , wherein said preceding step comprises the steps of: providing said serialized input data to a first input of an XOR gate having two inputs; providing the output from said XOR gate to the input of a D-flip flop whose clock input operates at said master clock rate; and providing the output from said D-flip flop to the second input of said XOR gate, wherein said output from said D-flip flop is a precoded data signal.
Claim 14
Dependent Claim
19 words
The method according to claim 10 , wherein said delayed clock signal generating step generates four delayed clock signals.
Claim 15
Dependent Claim
134 words
The method according to claim 12 , wherein said delayed clock signal selecting step comprises the steps of: if the current precoded data bit equals zero, selecting no delayed clock signal; and if the current precoded data bit equals one, selecting a delayed clock signal based on the values of the previous two precoded data bits, wherein: a first delayed clock signal is selected when the previous two precoded data bits both equal zero; a second delayed clock signal is selected when the previous two precoded data bits equal a zero and a one, respectively; a third delayed clock signal is selected when the previous two precoded data bits equal a one and a zero, respectively; and a fourth delayed clock signal is selected when the previous two precoded data bits both equal one.
Claim 16
Dependent Claim
62 words
The method according to claim 10 , wherein said delayed clock signal generation step comprises the steps of: generating a ramp waveform; generating a threshold voltage; providing said threshold voltage to the non-inverting input of a comparator; and providing said ramp waveform to the inverting input of said comparator, wherein the output of said comparator is one of said delayed clock signals.
Claim 17
Dependent Claim
22 words
The method according to claim 14 , wherein said ramp waveform has a constant peak-to-peak voltage regardless of said master clock rate.
Claim 18
Dependent Claim
73 words
The method according to claim 15 , further comprising the steps of: time-interleaving said precoded data signal into odd and even data sequences each operating at half said master clock rate; and generating at least two odd and two even delayed clock signals, wherein said RZ signal is a combination of an odd RZ signal and an even RZ signal, said odd and even RZ signals operating at half said master clock rate.
Claim 19
Dependent Claim
64 words
The method according to claim 16 , wherein said time-interleaving step comprises the steps of: generating an odd clock signal and an even clock signal each operating at half the master clock rate; and providing said precoded data to an odd series of D-flip flops clocked by said odd clock signal and to an even,series of D-flip flops clocked by said even clock signal.
Claim 20
Independent Claim
101 words
A method of writing to a disk, said method comprising the steps of: serializing data operating at a master clock rate; time-interleaving said serialized data into odd and even data sequences each operating at half said master clock rate; generating an odd return-to-zero (RZ) signal and an even RZ signal, each RZ signal operating at half said master clock rate, said odd RZ signal based on said odd data sequence and said even RZ signal based on said even data sequence; and combining said odd and even RZ signals to create a combined RZ signal operating at said master clock rate.
Claim 21
Independent Claim
101 words
A method of writing to a disk, said method comprising the steps of: serializing data operating at a master clock rate; time-interleaving said serialized data into odd and even data sequences each operating at half said master clock rate; generating an odd return-to-zero (RZ) signal and an even RZ signal, each RZ signal operating at half said master clock rate, said odd RZ signal based on said odd data sequence and said even RZ signal based on said even data sequence; and combining said odd and even RZ signals to create a combined RZ signal operating at said master clock rate.
Claim 22
Dependent Claim
150 words
A hard disk drive recording system comprising: a circuit for generating a write precompensation signal having precompensation delay, said circuit comprising: a precoder for precoding serialized input data to generate a precoded data signal operating at a master clock rate; a delayed clock pulse selector for generating clock pulse selection signals based on said precoded data; a delayed clock pulse generator for generating at least two delayed clock signals, for selecting either none or one of said delayed clock signals according to said clock pulse selection signals, and for generating a return-to-zero (RZ) signal whose time periods comprise either a zero if no delayed clock signal is selected or a pulse of said selected delayed clock signal; and a non-return-to-zero (NRZ) modulator for generating said precompensation signal from said RZ signal, wherein the maximum precompensation delay of said precompensation signal is at least 50% of the master clock time period.
Claim 23
Dependent Claim
150 words
A hard disk drive recording system comprising: a circuit for generating a write precompensation signal having precompensation delay, said circuit comprising: a precoder for precoding serialized input data to generate a precoded data signal operating at a master clock rate; a delayed clock pulse selector for generating clock pulse selection signals based on said precoded data; a delayed clock pulse generator for generating at least two delayed clock signals, for selecting either none or one of said delayed clock signals according to said clock pulse selection signals, and for generating a return-to-zero (RZ) signal whose time periods comprise either a zero if no delayed clock signal is selected or a pulse of said selected delayed clock signal; and a non-return-to-zero (NRZ) modulator for generating said precompensation signal from said RZ signal, wherein the maximum precompensation delay of said precompensation signal is at least 50% of the master clock time period.
Claim 24
Dependent Claim
77 words
The circuit according to claim 19 , wherein said precoder comprises: a D-flip flop whose clock input operates at said master clock rate; an XOR gate, having said serialized input data as a first input and having the output of said D-flip flop as a second input, wherein the output of said XOR gate is provided to the data input of said D-flip flop and wherein the output of said D-flip flop is the precoded data signal.
Claim 25
Dependent Claim
134 words
The circuit according to claim 20 , wherein if the current-precoded data bit equals zero, said delayed clock pulse generator selects no delayed clock signal, and wherein if the current precoded data bit equals one, said delayed clock pulse generator selects one delayed clock signal based on the values of the previous two precoded data bits, wherein: a first delayed clock signal is selected when the previous two precoded data bits both equal zero; a second delayed clock signal is selected when the previous two precoded data bits equal a zero and a one, respectively; a third delayed clock signal is selected when the previous two precoded data bits equal a one and a zero, respectively; and a fourth delayed clock signal is selected when the previous two precoded data bits both equal one.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-10 | 2005-12-10 | 2006-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-10 | 2009-12-10 | 2010-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-10 | 2013-12-10 | 2014-06-11 | $7700.00 | Window Closed / Lapsed |