Improvements in or relating to data processing

Claim 2

The method of claim 1 further comprising the steps of: providing an AND output signal based on the logical AND of said OR output signal and said write mode signal; and applying said AND output signal to a flip-flop circuit.

Claim 3

The method of Claim 1 or Claim 2, wherein said step of providing the comparator signal comprises providing a comparator signal that is derived from said timing generator output signal.

Claim 4

The method of Claim 1 or Claim 2 wherein said step of providing the comparator signal comprises providing a signal derived from an output of said comparator.

Claim 8

The method of Claim 7 further comprising the steps of: providing a write mode signal; providing an AND output signal based on the logical AND of said OR output signal and said write mode signal; applying said AND output signal to a flip-flop circuit.

Claim 9

The method of Claim 7 or Claim 8, wherein said step of providing the comparator signal comprises providing a comparator signal that is derived from said timing generator output signal.

Claim 10

The method of Claim 7 or Claim 8, wherein said step of providing the comparator signal comprises providing a comparator signal that is derived from an output of said comparator.

Claim 14

The method of Claim 13 further comprising the step of: compensating said extended duty cycle clock signal to maintain a constant duty cycle over a broad frequency range of said clock signal.

Claim 15

The method of Claim 13 or Claim 14, wherein said step of providing said clock signal, said delayed clock signal, said extended duty cycle clock signal comprises providing differential signals.

Claim 16

A write precompensation circuit comprising: a clock generator for providing a clock signal; a timing generator circuit coupled to said clock generator for receiving said clock signal and for generating a timing generator output signal; a comparator circuit coupled to said timing generator circuit for receiving and performing a comparison on said timing generator output signal; a failsafe clock generator for receiving said clock signal for providing a failsafe clock signal based on the logical AND of said clock signal and a delayed write mode signal; and an OR gate coupled to said comparator circuit and to said failsafe clock generator for receiving a signal from said comparator, for receiving said failsafe clock signal, and for providing an OR output signal.

Claim 17

The write precompensation circuit of Claim 16 further comprising: means for generating write mode signal; an AND gate coupled to said OR gate and to said write mode signal generating means for receiving said OR output signal and said write mode signal and for providing an AND output signal; a flip-flop circuit coupled to said AND gate for receiving said AND output signal and for providing a flip-flop output signal.

Claim 18

The write precompensation circuit of Claim 16 or Claim 17, wherein said comparator signal is derived from said timing generator output signal.

Claim 19

The write precompensation circuit of Claim 16 or Claim 17, wherein said comparator signal is derived from said comparator output signal.

Claim 20

The write precompensation circuit of any of Claims 16 to 19 further comprising: a selection means coupled to said OR gate for selecting said OR output signal when a large amount of precompensation is required and for deselecting said OR output signal when a lesser amount of precompensation is required.

Claim 21

The write precompensation circuit of any of Claims 16 to 19, wherein said clock signal, said timing generator output signal, said delayed write mode signal, said failsafe clock signal, said OR output signal, said write mode signal, said AND output signal, and said flip-flop output signal are differential signals.

Claim 22

A write precompensation circuit comprising: a clock generating means for providing a clock signal; a timing generator circuit coupled to said clock generating means for receiving said clock signal and for providing a timing generator output signal; a comparator circuit coupled to said timing generator circuit for receiving and performing a comparison on said timing generator output signal; an opposite phase clock generating means for providing an opposite phase clock signal having a phase opposite that of said clock signal; a previous data bit storage means for storing a previous data bit and for providing a previous data bit signal; a first AND gate for receiving said opposite phase clock signal and said previous data bit signal and for providing a failsafe clock signal; and an OR gate for receiving a comparator signal from said comparator, for receiving said failsafe clock signal, and for providing an OR output signal.

Claim 23

The write precompensation circuit of Claim 22 further comprising: a write mode signal generating means for providing a write mode signal; a second AND gate for receiving said OR output signal and said write mode signal and for providing an AND output signal; a flip-flop circuit coupled to said second AND gate for receiving said AND output signal and for providing a flip-flop output signal.

Claim 24

The write precompensation circuit of Claim 22 or Claim 23, wherein said comparator signal is derived from said timing generator output signal.

Claim 25

The write precompensation circuit of Claim 22 or Claim 23, wherein said comparator signal is derived from said comparator output signal.

Claim 26

The write precompensation circuit of any of Claims 22 to 25 further comprising: a selection means coupled to said OR gate for selecting said OR output signal when a large amount of precompensation is required and for deselecting said OR output signal when a lesser amount of precompensation is required.

Claim 27

The write precompensation circuit of any of Claims 22 to 26, wherein said clock signal, said timing generator output signal, said opposite phase clock signal, said previous data bit signal, said failsafe clock signal, said OR output signal, said write mode signal, said AND output signal, and said flip-flop output signal are differential signals.

Claim 28

A write precompensation circuit comprising: a clock generating means for providing a clock signal; a delay means for delaying said clock signal and for producing a delayed clock signal; an OR gate for receiving said clock signal and said delayed clock signal and for providing an extended duty cycle clock signal.

Claim 29

The write precompensation circuit of Claim 28 further comprising; a compensation means for compensating said extended duty cycle clock signal to maintain a constant duty cycle over a broad frequency range of said clock signal.

Claim 30

The write precompensation circuit of claim 28 or Claim 29, wherein said clock signal, said delayed clock signal, said extended duty cycle clock signal are differential signals.

Claim 31

A write precompensation circuit comprising; a clock generating means for providing a first clock signal and a second clock signal, said first clock signal and said second clock signal being complementary; a first transistor coupled to said clock generating means for receiving said first clock signal and for providing a first transistor output signal; a second transistor coupled to said clock generating means for receiving said second clock signal and for providing a second transistor output signal; a previous data bit signal generating means for generating a previous data bit signal; a third transistor coupled to said first transistor, to said second transistor, and to said previous data bit signal generating means for receiving a previous data bit signal and for providing a logical AND function; a fourth transistor coupled to said first transistor for receiving said first transistor output signal and for providing a fourth transistor output signal; a fifth transistor coupled to said second transistor for receiving said second transistor output signal and for providing a fifth transistor output signal; an OR gate having a non-inverting first differential input, an inverting first differential input, a non-inverting second differential input, an inverting second differential input, a non-inverting differential output, and an inverting differential output, said non-inverting first differential input coupled to said fourth transistor for receiving said fourth transistor output signal and said inverting first differential input coupled to said fifth transistor for receiving said fifth transistor output signal.

Claim 32

The write precompensation circuit of Claim 31 further comprising; an AND gate having a non-inverting first differential AND gate input, an inverting first differential AND gate input, a non-inverting second differential AND gate input, an inverting second differential AND gate input, a non-inverting differential AND gate output, and an inverting differential AND gate output, said non-inverting first differential AND gate input coupled to said non-inverting differential OR gate output and said inverting first differential AND gate input coupled to said inverting differential OR gate output.

Claim 33

The write precompensation circuit of Claim 31 or Claim 32 further comprising; a flip-flop having a non-inverting differential flip-flop input and an inverting differential flip-flop input, said non-inverting differential flipflop input coupled to said non-invertinq differential AND qate output and said inverting differential flip-flop input coupled to said inverting differential AND gate output.

Claim 34

A write precompensation circuit comprising: a clock generating means for providing a first clock signal and a second clock signal, said first and second clock signals being complementary; a first transistor coupled to said clock generating means for receiving said first clock signal and for providing a first transistor output signal; a second transistor coupled to said clock generating means for receiving said second clock signal and for providing a second transistor output signal; a delay means coupled to said clock generating means for receiving said first clock signal and said second clock signal and for providing a delay output signal; a third transistor coupled to said delay means for receiving said delay output signal and for providing a logical OR function.

Claim 35

The write precompensation circuit of Claim 34, wherein said delay means comprises: a fourth transistor coupled to said clock generating means for receiving said first clock signal and for providing a fourth transistor output signal; and a fifth transistor coupled to said clock generating means for receiving said second clock signal and for providing a fifth transistor output signal.

Claim 36

The write precompensation circuit of Claim 35, wherein said delay means further comprises: a sixth transistor coupled to said fourth transistor for receiving said fourth transistor output signal and for providing a sixth transistor output signal; a seventh transistor coupled to said fifth transistor for receiving said fifth transistor output signal and for providing a seventh transistor output signal.

Claim 37

The write precompensation circuit of Claim 36, wherein said delay means further comprises: a current injecting means for injecting a current into said sixth transistor to prevent duty cycle variations over frequency of said first clock signal.

Claim 38

The write precompensation circuit of any of Claims 34 to 37, wherein said delay means further comprises: a first current source coupled to said first transistor; a second current source coupled to said second transistor; a first capacitor coupled in parallel across said first current source; a second capacitor coupled in parallel across said second current source.

Claim 39

The write precompensation circuit of any of Claims 34 to 38 further comprising: a digital-to-analog converter having a current output for providing a current for controlling the operation of said write precompensation circuit and a digital input for receiving digital information, said digital input comprising a node for conveying a most significant bit of said digital information; a logic gate having a non-inverting logic gate differential input, an inverting logic gate differential input, an enable input, and a non-inverting logic gate differential output, and an inverting logic gate differential output, said non-inverting logic gate differential input coupled to said clock generating means for receiving said first clock signal, said inverting logic gate differential input coupled to said clock generating means for receiving said second clock signal, said enable input coupled to said node for selectively enabling said logic gate based on a status of said most significant bit of said digital information.