Patent US6400540B1 successfully refreshed from Google Patents.
US6400540B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clamp circuit to prevent ESD damage to an integrated circuit
Assignee: SILIABLE Inc
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Filing: 2000-03-11
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Granted: 2002-06-04
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Expires: 2020-03-11
Abstract
Abstract In an integrated circuit device requiring electrostatic discharge (ESD) protection, a circuit is added between a power supply bus and a ground supply bus to shunt the ESD event current and thereby avoiding damage to the device. Specifically, the circuit uses bipolar junction transistors of the PNP type to shunt the supply buses. The emitter junctions are connected to the positive supply bus. The collector junctions are connected to the ground bus. The PNP transistors conduct when a control circuit senses an ESD event and increases the base current in the PNP transistor.
Inventors
- 👤 Jiashann Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:33
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D89/711
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
127 words
An electrostatic discharge event protection circuit for a CMOS integrated circuit, at least part of which is a circuit between one of the power supply buses and one of the ground supply buses comprising; a. first a PNP transistor with emitter connected to a power supply bus and collector connected to a ground supply bus and the base connected to an NMOS transistor; and b. second an NMOS transistor with drain connected to the first PNP transistor base and source connected to the ground supply bus and gate connected to a delay circuit; and c. third a delay circuit connected at least to the power and ground buses that provides a positive potential relative to the ground bus into the NMOS transistor gate during an ESD event.
Claim 2
Dependent Claim
127 words
An electrostatic discharge event protection circuit for a CMOS integrated circuit, at least part of which is a circuit between one of the power supply buses and one of the ground supply buses comprising; a. first a PNP transistor with emitter connected to a power supply bus and collector connected to a ground supply bus and the base connected to an NMOS transistor; and b. second an NMOS transistor with drain connected to the first PNP transistor base and source connected to the ground supply bus and gate connected to a delay circuit; and c. third a delay circuit connected at least to the power and ground buses that provides a positive potential relative to the ground bus into the NMOS transistor gate during an ESD event.
Claim 3
Dependent Claim
128 words
An electrostatic discharge event protection circuit for a CMOS integrated circuit, at least part of which is a circuit between one of the power supply buses and one of the ground supply buses comprising; a. first a PNP transistor with emitter connected to a power supply bus and collector connected to a ground supply bus and the base connected to a PMOS transistor; and b. second a PMOS transistor with source connected to the first PNP transistor base and drain connected to the ground supply bus and gate connected to a delay circuit; and c. third a delay circuit connected at least to the power and ground buses that provides a negative potential relative to the power supply bus into the PMOS transistor gate during an ESD event.
Claim 4
Dependent Claim
128 words
An electrostatic discharge event protection circuit for a CMOS integrated circuit, at least part of which is a circuit between one of the power supply buses and one of the ground supply buses comprising; a. first a PNP transistor with emitter connected to a power supply bus and collector connected to a ground supply bus and the base connected to a PMOS transistor; and b. second a PMOS transistor with source connected to the first PNP transistor base and drain connected to the ground supply bus and gate connected to a delay circuit; and c. third a delay circuit connected at least to the power and ground buses that provides a negative potential relative to the power supply bus into the PMOS transistor gate during an ESD event.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-03 | 2005-12-03 | 2006-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-03 | 2009-12-03 | 2010-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-03 | 2013-12-03 | 2014-06-04 | $7700.00 | Window Closed / Lapsed |