Digital clock/data signal recovery method and apparatus

Claim 2

A clock signal recovery apparatus for use in a receiver in a digital communications system, the clock signal recovery apparatus comprising: a lead/lag detector having two input terminals and an output terminal, a first input terminal being coupled to receive an incoming data signal; a signal processor having an input terminal coupled to receive an output signal from the lead/lag detector, and an output terminal carrying a signal indicating a lead or lag in a recovered clock signal; a selector having a plurality of input terminals respectively coupled to receive clock signals of the same frequency and having differing relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the lead/lag detector; the lead/lag detector being constructed to provide at the output of the lead/lag detector a sample of the recovered clock signal from the second input terminal of the lead/lag detector in response to at least one of a rising or falling edge of a data transition at the first input of the lead/lag detector; wherein the clock recovery apparatus is constructed so as to be capable of recovering a transmit clock signal from non-periodic data within the incoming data signal; a local oscillator having a fixed frequency at substantially a same frequency as the transmit clock signal of the non-periodic data; a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local oscillator; and wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion.

Claim 3

The apparatus of claim 1 , wherein the lead/lag detector is a D type flip-flop, and its clock input terminal is the first input terminal and its D input terminal is the second input terminal.

Claim 4

The apparatus of claim 2 , wherein a frequency of the clock signals coupled to the selector is approximately the same as that of the recovered clock signal.

Claim 5

The apparatus of claim 1 , wherein a frequency of the clock signals is f, there are n input terminals of the selector, and a delay difference between clock signals is 1/nf.

Claim 6

The apparatus of claim 1 , wherein the phase pump portion outputs an output signal indicating a phase change from the signal processor portion for a particular time period.

Claim 7

The apparatus of claim 1 , wherein the signal processor portion accumulates a plurality of lead or lag indicating signals from the lead/lag detector and determines if the accumulated plurality of the signals collectively leads or lags the recovered clock signal and thereby outputs the signal indicating the lead or lag in the recovered clock signal.

Claim 8

The apparatus of claim 6 , wherein the signal processor portion determines non-linearly if the accumulated plurality of output signals collectively lead or lag.

Claim 9

The apparatus of claim 7 , whereupon if the accumulated plurality of signals are determined to be lagging, the signal processor portion outputs a signal for selecting a clock signal having reduced delay, and if the accumulated plurality of signals are determined to be leading, the signal processor portion outputs a signal for selecting a clock signal having an increased delay.

Claim 10

The apparatus of claim 1 wherein the apparatus includes only digital logic elements.

Claim 11

The apparatus of claim 1 , wherein the lead/lag detector detects both rising and falling edges of incoming signal pulses.

Claim 14

The method of claim 11 , wherein the step of accumulating includes determining non-linearly if the accumulated detected phases collectively lag or lead the selected clock signal.

Claim 15

The method of claim 11 , wherein the step of detecting includes detecting a phase of both positive going and negative going edges of the received signal.

Claim 16

The method of claim 11 , wherein the step of accumulating includes counting a number of the detected signal edges that lag and a number of the detected signal edges that lead.

Claim 17

The method of claim 11 , wherein the plurality of clock signals has frequency f, there are n clock signals in the plurality, and a delay difference between clock signals is 1/nf.

Claim 18

A receiver apparatus for receiving clock and data signals in a digital communications system comprising: an equalizing and slicing portion which receives an incoming data signal and outputs a discrete level analog transition time signal; a clock recovery portion including: a lead/lag detector having two input terminals and an output terminal, a first input terminal being coupled to receive the discrete level analog transition time signal; a signal processor having an input terminal coupled to receive an output signal from the phase detector, and an output terminal carrying a signal indicating the amount of lead or lag in the recovered clock signal; a selector having a plurality of input terminal respectively coupled to receive clock signals having about the same frequency and having different relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the lead/lag detector; the lead/lag detector being constructed to provide at the output of the lead/lag detector a sample of the recovered clock signal from the second input terminal of the lead/lag detector in response to at least one of a rising or falling edge of a data transition at the first input of the lead/lag detector; wherein the clock recovery portion is constructed so as to be capable of recovering a transmit clock signal from a non-periodic incoming data signal; a local oscillator having a fixed frequency at substantially a same frequency as the transmit clock signal of the non-periodic data signal; a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of the substantially the same frequency from a single frequency of the local oscillator; and wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion; and a data recovery portion having a clock terminal coupled to receive the recovered clock signal, a data input terminal coupled to receive the incoming data signal, and an output terminal providing a recovered data signal.

Claim 19

A receiver apparatus for receiving clock and data signals in a digital communications system comprising: an equalizing and slicing portion which receives an incoming data signal and outputs a discrete level analog transition time signal; a clock recovery portion including: a lead/lag detector having two input terminals and an output terminal, a first input terminal being coupled to receive the discrete level analog transition time signal; a signal processor having an input terminal coupled to receive an output signal from the phase detector, and an output terminal carrying a signal indicating the amount of lead or lag in the recovered clock signal; a selector having a plurality of input terminal respectively coupled to receive clock signals having about the same frequency and having different relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the lead/lag detector; the lead/lag detector being constructed to provide at the output of the lead/lag detector a sample of the recovered clock signal from the second input terminal of the lead/lag detector in response to at least one of a rising or falling edge of a data transition at the first input of the lead/lag detector; wherein the clock recovery portion is constructed so as to be capable of recovering a transmit clock signal from a non-periodic incoming data signal; a local oscillator having a fixed frequency at substantially a same frequency as the transmit clock signal of the non-periodic data signal; a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of the substantially the same frequency from a single frequency of the local oscillator; and wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion; and a data recovery portion having a clock terminal coupled to receive the recovered clock signal, a data input terminal coupled to receive the incoming data signal, and an output terminal providing a recovered data signal.

Claim 20

The apparatus of claim 16 , wherein the data recovery portion is a D type flip-flop circuit.

Claim 21

The apparatus of claim 16 , wherein the lead/lag detector is a D type flip-flop circuit and its clock input terminal is the first input terminal and its D input terminal is the second input terminal.

Claim 22

The apparatus of claim 18 , wherein a frequency of the clock signals coupled to the selector is approximately the same as that of the recovered clock signal.

Claim 23

The apparatus of claim 16 , wherein a frequency of the clock signals is f, and there are n input terminals of the selector, and a delay difference between clock signal is 1/nf.

Claim 24

The apparatus of claim 16 , wherein the phase pump portion outputs an output signal indicating a phase change from the signal processor portion for a particular time period.

Claim 25

The apparatus of claim 21 , wherein the signal processor portion accumulates a plurality of lead or lag indicating signals from the lead/lag detector and determines if the accumulated plurality of the signals collectively leads or lags the recovered clock signal, and thereby outputs the signal indicating the lead or lag in the recovered clock signal.

Claim 26

The apparatus of claim 22 , wherein the signal processor portion determines non-linearly if the accumulated plurality of output signals collectively lead or lag.

Claim 27

The apparatus of claim 23 , whereupon if the accumulated plurality of signals are determined to be lagging, the signal processor portion outputs a signal for selecting a clock signal having reduced delay, and if the accumulated plurality of signals are determined to be leading, the signal processor portion outputs a signal for selecting a clock signal having an increased delay.

Claim 28

The apparatus of claim 16 wherein the apparatus includes only digital logic elements.

Claim 29

The apparatus of claim 16 , wherein the lead/lag detector detects both rising and falling edges of the incoming signal pulses.

Claim 30

A clock signal recovery apparatus for use in a receiver in a digital communications system, the clock signal recovery apparatus comprising: a) a lead/lag detector comprising first and second input terminals and an output terminal, the first input terminal being adapted to receive a data signal having an embedded clock; b) a signal processor comprising an input terminal coupled to the output terminal of the lead/lag detector, the signal processor being capable of providing a control signal at the signal processor output terminal responsive to signals at the output terminal of the lead/lag detector; c) a selector having a plurality of input terminals adapted to receive a plurality of phase delayed clock signals, the selector comprising a control terminal coupled to the output terminal of the signal processor, the selector being capable of providing the recovered clock signal at an output terminal in response to the control signal, the output terminal of the selector being coupled to the second input terminal of the lead/lag detector; d) the lead/lag detector being constructed to compare at least one of a rising or falling edge of a data transition of the data signal with the reconstructed clock signal and to supply a fixed pulse width output at the output terminal of the lead/lad detector indicating a relative leading or lagging position of edge transitions of the reconstructed clock and the embedded clock, and wherein a leading or lagging indication is supplied only when the at least one of a rising or falling edge is detected at the first input of the lead/lag detector such that the embedded clock signal may be recovered without utilizing a reference clock signal; e) wherein the clock recovery apparatus is constructed so as to be capable of recovering the clock signal to be recovered from non-periodic data within the incoming signal; f) a local oscillator having a fixed frequency at substantially a same frequency as the clock signal to be recovered; g) a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local oscillator; and h) wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion.

Claim 31

A clock signal recovery apparatus for use in a receiver in a digital communications system, the clock signal recovery apparatus comprising: a) a lead/lag detector comprising first and second input terminals and an output terminal, the first input terminal being adapted to receive a data signal having an embedded clock; b) a signal processor comprising an input terminal coupled to the output terminal of the lead/lag detector, the signal processor being capable of providing a control signal at the signal processor output terminal responsive to signals at the output terminal of the lead/lag detector; c) a selector having a plurality of input terminals adapted to receive a plurality of phase delayed clock signals, the selector comprising a control terminal coupled to the output terminal of the signal processor, the selector being capable of providing the recovered clock signal at an output terminal in response to the control signal, the output terminal of the selector being coupled to the second input terminal of the lead/lag detector; d) the lead/lag detector being constructed to compare at least one of a rising or falling edge of a data transition of the data signal with the reconstructed clock signal and to supply a fixed pulse width output at the output terminal of the lead/lad detector indicating a relative leading or lagging position of edge transitions of the reconstructed clock and the embedded clock, and wherein a leading or lagging indication is supplied only when the at least one of a rising or falling edge is detected at the first input of the lead/lag detector such that the embedded clock signal may be recovered without utilizing a reference clock signal; e) wherein the clock recovery apparatus is constructed so as to be capable of recovering the clock signal to be recovered from non-periodic data within the incoming signal; f) a local oscillator having a fixed frequency at substantially a same frequency as the clock signal to be recovered; g) a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local oscillator; and h) wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion.

Claim 32

The apparatus of claim 27 wherein the lead/lag detector is a single D type flip-flop having a clock input, a D input, and an output, and wherein the first input terminal of the lead/lag detector is the clock input of the D flip-flop, and wherein the second input terminal of the lead/lag detector is the D input of the D flip-flop.

Claim 33

The apparatus of claim 28 further comprising a phase delay apparatus adapted to receive a single clock signal having approximately a same frequency as the recovered clock signal and being capable of generating phase delayed clock signals therefrom, and wherein the phase delay apparatus is capable of generating phase delayed clock signals each having the same frequency f, and wherein the selector comprises n input terminals, and wherein the delay difference between each of the plurality of phase delayed signals is 1/nf.

Claim 34

The apparatus of claim 28 wherein the digital signal processor is capable of accumulating a plurality output signals from the lead/lag detector and providing an output based on the accumulated output signals.

Claim 35

The apparatus of claim 30 wherein the digital signal processor is a non-linear digital signal processor.

Claim 36

The apparatus of claim 31 wherein the lead/lag detector is capable of providing, at the output terminal of the lead/lag detector, a sample derived from the recovered clock signal present at the second input terminal of the lead/lag detector, in response to one of leading or lagging edges of the data signal.

Claim 37

A clock signal recovery apparatus for use in a receiver in a digital communications system the clock signal recovery apparatus comprising: a phase detector having two input terminals and an output terminal, a first input terminal being coupled to receive an incoming signal having a clock signal to be recovered; a signal processor having an input terminal coupled to receive an output signal from the phase detector, and an output terminal carrying a signal indicating a lead or lag in a the recovered clock signal; a selector having a plurality of input terminals respectively coupled to receive clock signals of the same frequency and having differing relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the phase detector; wherein the phase detector is a D type flip-flop having a clock input terminal as the first input terminal and a D input as the second input terminal; wherein the clock recovery apparatus is constructed so as to be capable of recovering the clock signal to be recovered from non-periodic data within the incoming signal; a local oscillator having a fixed frequency at substantially a same frequency as the clock signal to be recovered; a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local oscillator; and wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion.

Claim 38

A clock signal recovery apparatus for use in a receiver in a digital communications system the clock signal recovery apparatus comprising: a phase detector having two input terminals and an output terminal, a first input terminal being coupled to receive an incoming signal having a clock signal to be recovered; a signal processor having an input terminal coupled to receive an output signal from the phase detector, and an output terminal carrying a signal indicating a lead or lag in a the recovered clock signal; a selector having a plurality of input terminals respectively coupled to receive clock signals of the same frequency and having differing relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the phase detector; wherein the phase detector is a D type flip-flop having a clock input terminal as the first input terminal and a D input as the second input terminal; wherein the clock recovery apparatus is constructed so as to be capable of recovering the clock signal to be recovered from non-periodic data within the incoming signal; a local oscillator having a fixed frequency at substantially a same frequency as the clock signal to be recovered; a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local oscillator; and wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion.

Claim 39

A clock signal recovery apparatus for use in a receiver of a digital transmit/receive circuit, the clock signal recovery apparatus comprising: a D-flip flop having a clock input terminal adapted to receive an incoming data signal; a non-linear digital signal processor having an input terminal coupled to receive an output signal from the D-flip flop, the non-linear digital signal processor being capable of outputting at an output terminal; a phase pump connected to the output terminal of the non-linear digital signal processor, the phase pump being capable of providing a latched N-bit output signal in response to the output terminal of the signal processor; a selector having a plurality of input terminals respectively coupled to receive clock signals of the same frequency and having differing relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the lead/lag detector; a lead/lag detector being constructed to provide at the output of the lead/lag detector a sample of the recovered clock signal from the second input terminal of the lead/lag detector in response to at least one of a rising or falling edge of a data transition at the first input of the lead/lag detector, the lead/lag detector comprising the D-flip flop; wherein the clock recovery apparatus is constructed so as to be capable of recovering the clock signal from non-periodic data within the incoming data signal; a local transmitter oscillator having a fixed frequency at substantially a same frequency as a transmit clock signal of the non-periodic data signal; and a phase delay circuit coupled between the local transmitter oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local transmitter oscillator.

Claim 40

A clock signal recovery apparatus for use in a receiver of a digital transmit/receive circuit, the clock signal recovery apparatus comprising: a D-flip flop having a clock input terminal adapted to receive an incoming data signal; a non-linear digital signal processor having an input terminal coupled to receive an output signal from the D-flip flop, the non-linear digital signal processor being capable of outputting at an output terminal; a phase pump connected to the output terminal of the non-linear digital signal processor, the phase pump being capable of providing a latched N-bit output signal in response to the output terminal of the signal processor; a selector having a plurality of input terminals respectively coupled to receive clock signals of the same frequency and having differing relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the lead/lag detector; a lead/lag detector being constructed to provide at the output of the lead/lag detector a sample of the recovered clock signal from the second input terminal of the lead/lag detector in response to at least one of a rising or falling edge of a data transition at the first input of the lead/lag detector, the lead/lag detector comprising the D-flip flop; wherein the clock recovery apparatus is constructed so as to be capable of recovering the clock signal from non-periodic data within the incoming data signal; a local transmitter oscillator having a fixed frequency at substantially a same frequency as a transmit clock signal of the non-periodic data signal; and a phase delay circuit coupled between the local transmitter oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local transmitter oscillator.